Lisa Su

Lisa Su (born 1969) is a Taiwan-born American electrical engineer and business executive who serves as chair, president, and chief executive officer of Advanced Micro Devices (AMD). She became president and chief executive in October 2014 and chair in February 2022. Her career combines research in semiconductor devices with the management of businesses producing processors and other computing technologies. (en.wikipedia.org)

Su earned three degrees at the Massachusetts Institute of Technology (MIT), conducting doctoral research on silicon-on-insulator transistors, before working at Texas Instruments, IBM, and Freescale Semiconductor. At AMD, her leadership has encompassed the introduction of Ryzen personal-computer processors and EPYC server processors, the acquisition of Xilinx, and expansion into high-performance computing and artificial intelligence accelerators. These developments connect her biography with the evolution of semiconductor research, processor competition, and computing infrastructure. (news.mit.edu)

Early life and education

Lisa Su was born in Tainan, Taiwan, in 1969 and immigrated to the United States with her family as a young child. She grew up in Queens, a borough of New York City. Her father was a statistician, and her mother worked as an accountant before becoming an entrepreneur. Su attended the Bronx High School of Science, where her education emphasized mathematics and science; an MIT profile also records her participation on the school’s mathematics team. She graduated in 1986. Later accounts of her childhood describe an interest in taking electronic equipment apart, but these stories are retrospective recollections rather than contemporary records of her early interests. (forbes.com)

Su entered the Massachusetts Institute of Technology (MIT) in the autumn of 1986 and studied electrical engineering. She completed her bachelor’s degree in 1990, her master’s degree in 1991, and her doctorate in 1994, all in electrical engineering at MIT. Her undergraduate education included participation in the institute’s 6A program, which provided industrial internship opportunities for electrical engineering and computer science students. Through that program, she worked at Analog Devices, gaining experience of engineering outside the university laboratory while continuing her academic studies. (news.mit.edu)

Her introduction to semiconductor research came during her first undergraduate year through MIT’s Undergraduate Research Opportunities Program (UROP). She worked in Professor Henry “Hank” Smith’s laboratory in Building 39, assisting a graduate student. In her 2026 MIT commencement address, Su recalled that her initial assignment involved making X-ray lithography mask blanks and working with small, two-inch wafers. She described entering a cleanroom in protective clothing, handling fragile wafers, and repeating experiments when the results differed from expectations. These tasks gave her direct experience of laboratory fabrication rather than only classroom instruction in electronic devices. (mtlsites.mit.edu)

Su subsequently identified this undergraduate laboratory work as the point at which she developed a sustained interest in semiconductors. The 2008 profile published by MIT’s Microsystems Technology Laboratories similarly connected her specialization in semiconductor devices to Smith’s laboratory and her internships at Analog Devices. During graduate study, she worked with Professor Dimitri Antoniadis and continued to combine device fabrication with experimental testing. Recalling that period in 2026, she described spending weeks making devices in the cleanroom, taking the wafers to a testing laboratory, and discussing unexpected behavior with Antoniadis before planning further experiments. Her doctoral education thus involved repeated cycles of fabrication, measurement, and revision; her dissertation, completed in 1994, concerned silicon-on-insulator transistors. (mtlsites.mit.edu)

Doctoral research on semiconductor devices

Su’s 1994 doctoral dissertation at the Massachusetts Institute of Technology was titled Extreme-submicrometer silicon-on-insulator (SOI) MOSFETs. Submitted to the Department of Electrical Engineering and Computer Science, it was supervised by Dimitri A. Antoniadis and James E. Chung. Its subject was the scaling of metal–oxide–semiconductor field-effect transistors fabricated in silicon-on-insulator structures, rather than conventional bulk-silicon devices. (dspace.mit.edu)

In an SOI transistor, a layer of insulating material—typically silicon dioxide—separates the active silicon film from the underlying substrate. This arrangement reduces parasitic source-and-drain junction capacitance and provides dielectric isolation between devices, but also introduces electrical and thermal design constraints. Su’s contemporaneous research examined how the silicon-film thickness, buried oxide, and device geometry affected operation as channel lengths approached a tenth of a micrometer. A central question was whether SOI could preserve gate control over the channel while delivering the anticipated performance advantages of smaller devices. (researchgate.net)

In the 1994 paper “Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET’s,” Su, J. B. Jacobs, Chung, and Antoniadis used two-dimensional numerical simulations to investigate short-channel effects. Their analysis showed that the buried oxide did not automatically confer superior electrostatic control: additional charge sharing through that layer meant that the SOI silicon film had to be considerably thinner than the junction depth of a comparable bulk device to reduce short-channel effects. The study identified viable designs for both fully depleted and partially depleted devices, while finding that manufacturing considerations near $0.1\,\mu\text{m}$ could favor partially depleted structures. These were coauthored findings, distinct from the individually authored dissertation. (researchgate.net)

Thermal behavior was another practical constraint. In “Measurement and modeling of self-heating in SOI nMOSFET’s,” published in January 1994, Su collaborated with Chung, Antoniadis, Kenneth E. Goodson, and Markus I. Flik. The researchers measured temperature increases exceeding $100\,\text{K}$ under static operating conditions. The buried oxide impeded heat removal, raising channel temperature and reducing carrier mobility. Their model related temperature rise to silicon thickness, buried-oxide thickness, and the distance between the channel and metal contacts; it also distinguished steady-state measurements from dynamic circuit operation, where channel temperatures could be substantially lower. (researchgate.net)

A separate MIT team result, announced on July 20, 1994, concerned transistors with $0.1\,\mu\text{m}$, or 100-nanometer, channel lengths. The conference paper’s authors were Hang Hu, Su, Isabel Yang, Antoniadis, and Henry I. Smith; it had been presented at the June 7–9 VLSI technology conference in Honolulu. The team used ion implantation to limit drain-induced barrier lowering and X-ray lithography to pattern the gate. MIT reported that the devices achieved the highest electron velocity then reported for a given degree of barrier lowering. That claim described a specific performance–electrostatics trade-off in collaborative experimental work, not a general claim that Su alone had invented a faster transistor or SOI technology. (news.mit.edu)

Texas Instruments and IBM

Su worked at Texas Instruments from 1994 to 1995 as a member of the technical staff in its Semiconductor Process and Device Center. She joined IBM in 1995, beginning a period of employment that lasted until June 2007. Her positions there extended from semiconductor engineering to management of emerging products, technology-development partnerships, and research operations. Freescale’s subsequent regulatory filings identify her IBM leadership posts as director of Emerging Products, vice president of Technology Development and Alliances, and vice president of Semiconductor Research and Development. (amd.com)

At IBM, Su participated in the development of copper interconnects, the microscopic wiring that connects transistors within an integrated circuit. Replacing aluminum-based wiring with copper addressed a growing limitation of chip miniaturization: increasingly narrow wires imposed electrical resistance even as transistors became smaller and faster. Copper offered lower resistance, greater allowable current density, and scope for further reductions in wiring dimensions. Its integration nevertheless required protection against copper diffusion into surrounding materials, which could damage semiconductor devices. IBM’s manufacturing solution combined diffusion barriers, electroplating, and a damascene process in which metal filled patterned recesses in insulating layers. These were collective developments involving researchers in materials, chemistry, device engineering, and manufacturing, rather than an invention attributable to Su alone. (research.ibm.com)

Her documented technical contribution includes coauthorship of the 1997 International Electron Devices Meeting paper “Full copper wiring in a sub-0.25 μm CMOS ULSI technology.” The paper lists 15 authors, including D. Edelstein, J. Heidenreich, R. D. Goldblatt, C. Uzoh, and L. Su. It described copper wiring integrated with sub-0.25-micrometer CMOS technology operating at 1.8 volts. The implementation supported up to six copper wiring levels, with a minimum metal-contacted pitch of 0.63 micrometers, while retaining tungsten for local interconnects and contacts. Testing included functional 288 K static-memory chips packaged into product modules and subjected to reliability evaluation. The authors reported that the integrated copper wiring met or exceeded the standards of IBM’s aluminum-based reference technology. (research.ibm.com)

Su’s later IBM appointments expanded her responsibilities beyond individual device and process development. By October 2005, she had been named vice president of the Semiconductor Research and Development Center. Contemporary reporting placed its staff at approximately 1,000, with substantial operations in East Fishkill, New York; her remit also included semiconductor research and development in Albany. She reported to Doug Grose, IBM’s general manager for technology development and manufacturing. (edn.com)

In that position, Su was responsible for the strategic direction of IBM’s silicon technologies, joint development alliances, and semiconductor research and development operations. The role combined oversight of internal engineering with coordination of technology programs involving external partners. She remained at IBM until June 2007, when she moved to Freescale Semiconductor as senior vice president and chief technology officer. (amd.com)

Technology and business leadership at Freescale

On June 18, 2007, Freescale Semiconductor announced Su’s appointment as senior vice president and chief technology officer, following her departure from IBM. Her responsibilities covered global technical research and development and the company’s technology roadmap. The position placed her in charge of technology planning across a semiconductor supplier serving automotive, consumer, industrial, networking, and wireless markets, rather than a single processor family. Freescale’s chairman and chief executive, Michel Mayer, presented the appointment as bringing together her experience in technology development, product management, and strategic alliances. (chron.com)

In September 2008, Su became senior vice president and general manager of Freescale’s Networking and Multimedia group. The transition involved a period of overlapping responsibilities: Freescale’s subsequent regulatory filings recorded her CTO tenure as June 2007 through August 2009, when Ken Hansen assumed that position. As general manager, she was responsible for global strategy, marketing, and engineering for the embedded communications and applications-processor business. This broadened her remit from company-wide technology direction to managing the relationship between product development, customer requirements, and the markets in which those products competed. (investors.nxp.com)

The communications side of the business included PowerQUICC and QorIQ networking processors, alongside digital signal processors. These products performed different functions within communications equipment: networking processors controlled and manipulated data and network interfaces, while signal processors handled computationally intensive, real-time workloads such as wireless infrastructure and voice or video processing. Their customers built equipment including cellular base stations, switches, routers, and media gateways. The multimedia side included the i.MX applications-processor family, used to support operating systems and multimedia functions in portable computing and consumer devices. Together, these businesses extended Su’s responsibilities across infrastructure equipment and end-user products, rather than a single application market. (sec.gov)

Freescale’s StarCore signal-processing business provides a specific example of product investment during her tenure. A company brochure published in November 2010 linked the management changes involving chief executive Rich Beyer and Su in 2008 to increased investment in StarCore architecture and development tools. It described an initial emphasis on wireless base stations, followed by expansion into medical, aerospace, defense, and test-and-measurement applications. The SC3850 processor core, released in 2009, became the building block for the MSC8156 six-core signal processor. These were company development programs under the group’s management, not technologies attributed to Su as an individual inventor. (nxp.com)

Joining AMD and becoming chief executive

Lisa Su joined Advanced Micro Devices (AMD) on January 3, 2012, as senior vice president and general manager of Global Business Units, reporting to president and chief executive officer Rory Read. Her appointment had been announced on December 15, 2011. Based in Austin, Texas, she oversaw businesses serving client computing, commercial systems, consumer and professional graphics, and game consoles. Her remit covered product-business execution, including strategy, product definition, and business plans, rather than research management alone. She also became responsible for alliances with software developers intended to ensure that applications could use AMD’s hardware capabilities. AMD’s subsequent proxy statement confirmed both her January 3 start date and these business and software-partnership responsibilities. (globenewswire.com)

On June 12, 2014, AMD announced Su’s promotion to chief operating officer as part of a reorganization implemented on July 1. Continuing to report to Read, she took responsibility for bringing previously separate business units, sales, and global operations into one organization covering product strategy, execution, sales, and operations. The restructuring established two expanded business groups. Computing and Graphics combined client processors with consumer and professional graphics, including related engineering and sales functions; chief sales officer John Byrne became its senior vice president and general manager, reporting to Su. Enterprise, Embedded and Semi-Custom brought together server, embedded, dense-server, and semi-custom businesses, with Su initially serving as acting head. AMD presented the arrangement as a means of accelerating decisions and coordinating its established personal-computer businesses with expansion into other markets. (ir.amd.com)

On October 8, 2014, AMD’s board appointed Su president, chief executive officer, and a director, effective immediately. She succeeded Read in all three positions. The announced transition provided for Read to remain with AMD in an advisory capacity through the end of 2014. Board chairman Bruce Claflin described the succession planning as a joint effort between Read and the board. Su’s appointment therefore followed nearly three years of responsibility for AMD’s product businesses and approximately three months in the reorganized chief operating officer role. Her accompanying statement emphasized developing technologies and products for a diversified set of markets while building on the restructuring undertaken during Read’s tenure. (ir.amd.com)

The succession announcement distinguished the operational changes already made from the growth the new leadership was expected to pursue. AMD reported that operating expenditures had fallen by approximately 30 percent since 2012, cash had been maintained near $1 billion, and its debt schedule had been revised so that no significant maturities fell due before 2019. These were company-reported conditions at the handover, not results attributed to Su’s subsequent chief-executive tenure. (ir.amd.com)

In TIME’s December 2024 retrospective, Su’s turnaround strategy was described in three parts: developing stronger products, concentrating on customer relationships, and simplifying the business. The profile reported that she rejected a proposed shift toward low-power phone processors in favor of AMD’s capabilities in high-performance processors. These were stated strategic choices about where to concentrate development resources and commercial attention, rather than evidence that recovery was assured when she became chief executive. (time.com)

Processor strategy and the Ryzen and EPYC launches

During Su’s early tenure as chief executive, AMD’s processor roadmap centered on Zen, a processor-core architecture used across distinct product families: Ryzen for personal computers and EPYC for servers. The architecture supplied the processing cores, while individual products differed in core counts, memory capabilities, input/output resources, and platforms. Zen’s development preceded her appointment as chief executive: at the February 2017 Ryzen announcement, Su described a project begun four years earlier. AMD’s May 16, 2017 Financial Analyst Day presentation set out a strategy of extending this architectural foundation across premium desktops, notebooks, commercial PCs, and data centers, rather than confining it to a single market. (ir.amd.com)

The first Ryzen 7 desktop processors became available on March 2, 2017, following the opening of preorders on February 22. The three initial models—1800X, 1700X, and 1700—each provided eight cores and sixteen processing threads on the AM4 platform, with suggested US prices of $499, $399, and $329 respectively. They targeted gamers, content creators, and enthusiasts. AMD promoted their multithreaded performance through demonstrations of rendering and video-transcoding workloads; its comparisons with Intel processors were company-conducted tests under specified configurations, not evidence of superiority in every application. The launch depended on a wider platform effort, including motherboard suppliers and system builders, alongside AMD’s processor engineering. (ir.amd.com)

Expansion during 2017 involved both additional processor tiers and adoption by large PC manufacturers. By Computex in May, AMD had launched Ryzen 5 alongside Ryzen 7 and displayed systems including Acer’s Aspire GX-281, Dell’s Inspiron Gaming Desktop and Inspiron 27 7000 all-in-one, and Lenovo’s IdeaCentre desktops. Su presented the event as an opportunity to show Ryzen-based products from Acer, Asus, Dell, HP, and Lenovo. AMD also announced a broader segmentation of the family: Threadripper would address high-end desktops with up to sixteen cores and thirty-two threads, while planned mobile processors would combine four Zen cores with Vega graphics. These were roadmap announcements at that point, distinct from the desktop processors already available. (ir.amd.com)

On June 20, 2017, AMD launched the EPYC 7000 series for enterprise and cloud-computing servers. With up to thirty-two Zen cores, EPYC targeted both one-socket and two-socket systems; Su emphasized the ability to serve substantial workloads with one socket while also scaling to two. Server-market entry required more than processor availability. HPE, Dell, Lenovo, Supermicro, and other manufacturers introduced EPYC-based products, while Microsoft, Red Hat, and VMware demonstrated operating-system or virtualization support. Cloud customers made differentiated commitments: Baidu said deployment would begin with the launch, whereas Microsoft Azure stated its intention to offer EPYC to customers. These announcements documented an emerging hardware, software, and customer ecosystem, rather than uniform deployment across all participating organizations. (ir.amd.com)

Subsequent financial reports show the product families’ commercial development without isolating Su’s individual contribution. For 2023, AMD reported total revenue of $22.68 billion, down 4% from 2022, and GAAP net income of $854 million. Data Center revenue rose 7% to approximately $6.5 billion, which AMD attributed principally to higher sales of fourth-generation EPYC processors and Instinct graphics accelerators; that segment therefore cannot be treated as EPYC-only revenue. Client revenue fell 25% to approximately $4.7 billion amid a declining PC market, although fourth-quarter Client revenue increased 62% year over year, driven primarily by Ryzen 7000 sales. The figures distinguish longer-term portfolio expansion from the different demand conditions affecting servers and PCs. (amd.com)

Acquisitions and expansion of AMD’s portfolio

On October 27, 2020, AMD and Xilinx announced a definitive agreement for AMD to acquire Xilinx in an all-stock transaction valued at approximately $35 billion at announcement. Under the agreement, Xilinx shareholders would receive a fixed 1.7234 AMD shares for each Xilinx share. Su was to remain chief executive of the combined company. The announcement did not constitute completion: the companies remained independent while shareholder approvals, regulatory approvals, and other closing conditions were pending. Although initially expected to close by the end of 2021, the acquisition was completed on February 14, 2022. At closing, shareholders received the agreed share exchange, with cash replacing fractional shares, and Xilinx ceased trading separately on Nasdaq. The $35 billion figure therefore describes the announced valuation rather than a fixed cash purchase price. (ir.amd.com)

The acquisition extended AMD’s portfolio beyond central processing units and graphics processing units to include field-programmable gate arrays (FPGAs), adaptive systems-on-chip, and associated development software. An FPGA provides programmable hardware circuitry that can be reconfigured after manufacture; adaptive systems-on-chip combine programmable logic with processor systems and, in some families, specialized acceleration engines. These capabilities support application-specific data paths and embedded processing rather than relying exclusively on software executed by general-purpose processors. Xilinx also brought established business in communications, automotive, industrial, aerospace, and defense markets. Su presented the combination as a way to broaden AMD’s products and customer base across cloud, edge, and end-device computing, rather than simply expand its existing processor lines. (amd.com)

At completion, former Xilinx chief executive Victor Peng became president of AMD’s newly formed Adaptive and Embedded Computing Group. Its assigned responsibilities included FPGA, adaptive system-on-chip, and software roadmaps, with access to AMD’s CPU and GPU technologies for broader system offerings. On the same date, February 14, 2022, AMD’s board elected Su chair while she retained her existing positions as president and chief executive officer. The chair appointment added a board-leadership role; it was not another appointment to the chief executive position. John Caldwell, who had chaired the board since May 2016, became lead independent director, while former Xilinx directors Jon Olson and Elizabeth Vanderslice joined AMD’s board. (ir.amd.com)

AMD pursued a separate expansion into data-center infrastructure services through Pensando Systems. It announced an agreement to acquire Pensando on April 4, 2022, for approximately $1.9 billion before working-capital and other adjustments, and completed the transaction on May 26, 2022, reporting approximately the same value. Pensando’s distributed-services platform paired a programmable packet processor, described at closing as a data processing unit (DPU), with software for networking, security, storage, and related infrastructure functions. Its mechanism was to offload such work from server CPUs to processors distributed through the network. AMD identified existing deployments at Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle Cloud. The Pensando team joined the Data Center Solutions Group led by Forrest Norrod; Su described its hardware and software as complementing AMD’s compute processors with additional data-transfer, security, and analytics capabilities. (ir.amd.com)

Supercomputing and artificial intelligence

During Su’s tenure as chief executive, AMD supplied the processors and accelerators for Frontier, developed with Hewlett Packard Enterprise (HPE) and Oak Ridge National Laboratory (ORNL). Its 9,472 compute nodes each combined one third-generation AMD EPYC CPU with four Instinct MI250X GPU accelerators, housed in 74 HPE Cray EX cabinets. On the TOP500 list announced on May 30, 2022, Frontier ranked first with a measured High Performance Linpack result of 1.102 exaflops—approximately $1.1 \times 10^{18}$ floating-point operations per second—making it the first system to cross the exascale threshold on that benchmark. This was a measured benchmark result, rather than its theoretical peak performance. (ornl.gov)

Su represented AMD at ORNL’s August 17, 2022, celebration of Frontier alongside HPE chief executive Antonio Neri and government and laboratory officials. Her remarks emphasized the long-term public–private partnership and the machine’s intended applications in physics, medicine, climate research, and energy. The laboratory attributed the system’s development to teams across ORNL, HPE, AMD, and the Department of Energy; Su’s documented role at the ceremony was that of a corporate partner representative, not an individual system designer. (ornl.gov)

On December 6, 2023, AMD announced the availability of two distinct Instinct MI300 products. The MI300X was a GPU accelerator aimed at generative AI, including large language model training and inference. It incorporated 192 GB of HBM3 high-bandwidth memory; an eight-accelerator platform provided approximately 1.5 TB of aggregate accelerator memory. The MI300A instead combined 24 Zen 4 CPU cores, CDNA 3 GPU resources, and 128 GB of HBM3 in one package. Its unified memory and cache resources allowed CPU and GPU components to work within an integrated memory arrangement, targeting high-performance scientific computing as well as AI. The distinction was therefore architectural, rather than simply a difference in accelerator speed or memory capacity. (ir.amd.com)

The launch also introduced ROCm 6, AMD’s open-source software stack for its accelerators. AMD described support for frameworks and model ecosystems including PyTorch, TensorFlow, and Hugging Face, alongside features such as FlashAttention and vLLM. Its software partnerships addressed both training and deployment: MosaicML used ROCm to enable language-model training on Instinct accelerators, while Lamini worked on enterprise language-model applications. At the accompanying event, Microsoft described deploying MI300X accelerators for Azure’s ND MI300x v5 virtual machines, and Meta said it was adding MI300X hardware and ROCm 6 for inference workloads. Oracle’s proposed cloud offerings and several server manufacturers’ integrations were presented as plans, not as evidence that all those services and systems were already generally available. (ir.amd.com)

The MI300A’s announced supercomputing application subsequently produced a separately measured result. At the December 2023 launch, AMD described Lawrence Livermore National Laboratory’s El Capitan as an expected future exascale system. In November 2024, the laboratory reported that the HPE-and-AMD system had achieved 1.742 exaflops on High Performance Linpack and ranked first on that month’s TOP500 list. El Capitan used MI300A packages integrating CPU cores, GPU cores, and high-bandwidth memory; its verified benchmark result was distinct from both the earlier deployment forecast and its higher theoretical peak performance. (ir.amd.com)

Industry service and educational philanthropy

On November 20, 2025, the Semiconductor Industry Association (SIA) announced Su’s election as chair of its board of directors for the 2026 leadership year. SIA is an industry representative organization rather than a government agency: it works with Congress, the executive branch, and international stakeholders on policies affecting semiconductor manufacturing, design, and research. At the time of the announcement, the association stated that its membership represented 99 percent of the United States semiconductor industry by revenue and nearly two-thirds of non-U.S. chip firms. Su’s board chairmanship therefore concerned collective industry policy, distinct from her executive and governance responsibilities at AMD. (semiconductors.org)

Su’s federal advisory service included appointment by President Joe Biden to the President’s Council of Advisors on Science and Technology (PCAST), announced on September 22, 2021. The council draws on experts outside the federal government to advise the president on science, technology, innovation, and the scientific information needed for public policy. Its remit spans subjects including education, energy, economic development, and national security; it is not an AMD commercial body. On March 25, 2026, President Donald Trump also named Su among the initial appointments to his administration’s PCAST, co-chaired by David Sacks and Michael Kratsios. (presidency.ucsb.edu)

A documented example of Su’s council work was her co-leadership, with NVIDIA chief scientist William Dally, of PCAST’s semiconductor working group. At the council’s September 7, 2022 public meeting, they presented Revitalizing the U.S. Semiconductor Ecosystem, addressing implementation of the $11 billion appropriated for semiconductor research and development under the CHIPS and Science Act. The group proposed a public–private National Semiconductor Technology Center, geographically distributed prototyping facilities, and a national microelectronics education and training network. Its recommendations included approximately $1 billion over five years for educational laboratories, curricula, and faculty, together with approximately 2,500 scholarships and research assistantships annually through center-funded research. These were collective policy recommendations approved by PCAST, not funding commitments made by Su or AMD. (bidenwhitehouse.archives.gov)

Su’s educational philanthropy has included support for the Massachusetts Institute of Technology and its nanoscale research community. In 2018, she established the Lisa Su Fellowship Fund to support female graduate students with demonstrated progress and accomplishments in nanotechnology. On April 7, 2022, MIT announced that Building 12, home to MIT.nano, would be named the Lisa T. Su Building in recognition of her gift. MIT identified her as its first female graduate to make a gift for a building bearing her own name; the naming ceremony was scheduled for May 14. Her university service also included ten years on the Electrical Engineering and Computer Science Visiting Committee. (news.mit.edu)

The building had opened in 2018 as a shared facility for nanoscale science and engineering, rather than as a laboratory confined to one department. By the 2022 naming announcement, it served researchers from more than three dozen MIT departments, laboratories, and centers, alongside external users. MIT.nano’s access model permits faculty, students, and qualified researchers from other universities, industry, and government to undertake projects in specialized environments with technical staff support. In explaining her support, Su emphasized hands-on learning and the facility’s role in educating future technologists and researchers. (news.mit.edu)

Professional recognition and honors

Su was elevated to Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2009. Fellowship is a professional membership distinction, rather than a named medal or a prize for a particular publication. IEEE’s evaluation process considers documented accomplishments and their impact on engineering, science, and technology; its rules cap annual elevations at 0.1 percent of the preceding year’s voting membership. Su’s elevation preceded her appointment as AMD chief executive in 2014 and was recorded in industry biographies alongside her authorship of more than 40 technical articles. (semiconductors.org)

In 2021, she received the IEEE Robert N. Noyce Medal, sponsored by Intel. Its official citation recognized her “leadership in ground-breaking semiconductor products and successful business strategies that contributed to the strength of the microelectronics industry.” The distinction therefore explicitly encompassed both semiconductor products and business leadership, rather than recognizing a single device invention. Su was the first woman to receive the medal and donated its US$20,000 cash prize to the IEEE Women in Engineering Fund through the IEEE Foundation. The medal was separate from the Semiconductor Industry Association’s Robert N. Noyce Award, for which she had been selected in 2020; the similarly named honors were conferred by different organizations in different years. (spectrum.ieee.org)

Su was elected to the National Academy of Engineering in 2018. She subsequently became a member of the American Academy of Arts and Sciences, whose election records place her in the class of 2020, under Engineering and Technology within the Mathematical and Physical Sciences. Her Academy induction took place on September 10, 2022, at Kresge Auditorium at the Massachusetts Institute of Technology, in a ceremony for members elected in 2020 and 2021. She spoke on behalf of the Mathematical and Physical Sciences class. The election year and the later ceremony date thus refer to distinct stages of her membership. (semiconductors.org)

Her business honors included the Franklin Institute’s 2024 Bower Award for Business Leadership. The institute’s citation emphasized her leadership of AMD, its expansion in high-performance and adaptive computing, and her support for diversity and women in technology. This was the institute’s business-leadership award, not its separate Bower Award and Prize for Achievement in Science. The business award’s selection procedure involves a committee of previous laureates, trustees, and other leaders in science, technology, and business, with final approval by the institute’s board of trustees. (fi.edu)

TIME named Su its 2024 CEO of the Year, publishing Billy Perrigo’s profile on December 10, 2024. The designation was a media honor, distinct from professional fellowship, academy election, or an engineering medal. TIME also featured her in its December 11 “A Year in TIME” celebration in New York City, where she discussed the semiconductor industry with editor-in-chief Sam Jacobs. The CEO designation formed part of the magazine’s year-end recognition of leaders and was separate from its Person of the Year selection. (time.com)

References

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48. Find Out Who Received a 2021 IEEE Major Awardspectrum.ieee.org
49. Lisa T. Su Wins 2021 IEEE Robert N. Noyce Medal: She is the first woman to receive the honorieeexplore.ieee.org
50. Lisa Su | The Franklin Institutefi.edu
51. Bower Award for Business Leadership - Nominationsfi.edu