Complementary Metal–Oxide–Semiconductor

Complementary metal–oxide–semiconductor (CMOS) is a circuit-design approach and integrated-circuit fabrication technology that uses complementary n-channel and p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs). Its characteristic digital circuits provide a conducting path to one supply rail while interrupting the path to the other, greatly reducing steady-state power consumption. CMOS is a foundational technology for digital electronics and also supports analog, mixed-signal, radio-frequency, and imaging devices. (ocw.mit.edu)

Meaning and physical basis

The word complementary refers to the use of two transistor types with opposite control behavior. In conventional enhancement-mode devices, an n-channel MOSFET conducts when its gate is sufficiently positive relative to its source; a p-channel MOSFET conducts when its gate is sufficiently negative relative to its source. Their combination allows circuits to switch outputs between high and low voltage levels without requiring a continuously conducting load. (ocw.mit.edu)

A MOSFET contains a gate, source, drain, and body. The gate is separated from the semiconductor by a thin insulating dielectric. Gate voltage creates an electric field that controls conduction in the channel between source and drain. In silicon devices, n-channel conduction is associated primarily with electrons, and p-channel conduction with electron holes. The gate draws little steady-state current, although changing its voltage requires charging or discharging capacitance. (ocw.mit.edu)

The name metal–oxide–semiconductor describes the historical gate structure, not an invariant materials recipe. Many generations used polysilicon rather than metal gates. More advanced processes introduced metal gates together with high-permittivity, or high-k, dielectrics, including hafnium-based materials, instead of relying solely on silicon dioxide. These devices remain part of CMOS technology. (live.ocw.mit.edu)

The CMOS inverter

The simplest static CMOS logic gate is an inverter, which implements logical NOT. It contains one p-channel transistor connected between the positive supply, conventionally denoted (V_{DD}), and the output, and one n-channel transistor connected between the output and the lower supply, commonly ground. Their gates share the input connection. (ti.com)

In either stable state, one transistor is off, so the ideal circuit has no direct-current path between its supply rails. Real devices have leakage, but the absence of an intentional steady conducting path is the central reason for CMOS’s low static power consumption. During a transition, both transistors can briefly conduct, and current also flows to change the output voltage. (ti.com)

CMOS gates also regenerate logic levels: valid inputs produce outputs close to the appropriate supply rail. Their voltage-transfer characteristics establish noise margins, the ranges of electrical disturbance that can be tolerated without changing the interpreted logic state. Switching behavior therefore depends on defined input and output voltage ranges, not simply on an abstract division between zero and one. (ocw.mit.edu)

Logic networks and storage

More complex static CMOS gates use a p-channel pull-up network and an n-channel pull-down network. The networks are complementary: for each valid, stable input combination, one connects the output to its supply rail while the other interrupts the opposite connection. Series and parallel arrangements implement operations described by Boolean algebra. (ocw.mit.edu)

For example:

• A two-input NAND gate has two n-channel transistors in series and two p-channel transistors in parallel. Its output is low only when both inputs are high.
• A two-input NOR gate has two n-channel transistors in parallel and two p-channel transistors in series. Its output is high only when both inputs are low.

NAND and NOR are natural single-stage static CMOS functions. AND and OR are commonly obtained by adding an inverter to the corresponding inverting gate. (ocw.mit.edu)

Complementary devices can also form a transmission gate: an n-channel and a p-channel transistor connected in parallel and controlled by opposite-polarity signals. Their conductances complement one another across the signal-voltage range, producing a more effective switch than either device alone. Transmission gates are used in signal switches and multiplexers. (ti.com)

CMOS supports storage as well as combinational logic. A conventional six-transistor static random-access memory (SRAM) cell contains two cross-coupled inverters and two access transistors. The inverters form a bistable circuit that stores one bit, while the access transistors connect it to the memory’s bit lines for reading and writing. “Static” means that the stored state does not require periodic refresh while the cell remains powered; it does not mean that the memory is nonvolatile. (ocw.mit.edu)

Power consumption

CMOS power consumption has several components:

• Capacitive switching power: current charges and discharges transistor and interconnect capacitances.
• Short-circuit power: both transistor networks may conduct briefly during a transition.
• Static power: leakage and any other continuously operating circuit elements draw current even without logic transitions. (ti.com)

For ordinary, non-energy-recovering CMOS switching, the capacitive component is commonly approximated by

[ P_{\mathrm{switching}}\approx \alpha C_{\mathrm{eff}}V_{DD}^{2}f, ]

where (C_{\mathrm{eff}}) is the effective switched capacitance, (f) is the reference operating frequency, and (\alpha) is the average number of charging events per reference cycle. The activity convention matters: counting both rising and falling transitions changes the corresponding prefactor. The equation expresses why voltage, switching activity, frequency, and electrical loading strongly affect power consumption. (ocw.mit.edu)

Static leakage power can be approximated by (V_{DD}I_{\mathrm{leak}}). Leakage includes reverse-biased junction current and, in sufficiently thin gate dielectrics, current associated with quantum tunneling. Consequently, “low-power CMOS” does not mean zero-power CMOS, and stopping switching does not eliminate all consumption. (ti.com)

Fabrication and transistor architectures

CMOS fabrication creates both transistor polarities on a common substrate. In a conventional n-well process, n-channel devices occupy a p-type silicon region, while p-channel devices occupy n-type wells. Doping establishes the required semiconductor regions, and reverse-biased p–n junctions help isolate them electrically. Well and substrate contacts control the body potentials. (ti.com)

Manufacturing involves repeated patterning and processing steps. Photolithography defines selected regions; implantation introduces dopants; deposition, etching, and related operations build transistor structures and interconnects. Many devices are formed together on a wafer rather than assembled individually. (download.intel.com)

CMOS is not restricted to a flat, planar transistor geometry. Important device architectures include:

• Planar MOSFETs, with a channel near the substrate surface beneath the gate.
• FinFETs, whose channel forms a raised fin controlled by the gate on multiple sides.
• Gate-all-around transistors, whose gate surrounds a channel implemented as a wire, sheet, or ribbon.

These architectures change gate control and device geometry without abandoning the complementary use of n-channel and p-channel transistors. Advanced manufacturing platforms therefore describe both FinFET-based and gate-all-around implementations as CMOS technologies. (community.intel.com)

Historical development

In 1963, Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor presented complementary MOS circuitry with extremely low standby power. Wanlass filed a related patent that year. RCA subsequently pioneered commercial CMOS production under the name COS/MOS, initially emphasizing low-power applications. In 1968 it introduced the first members of its CD4000 general-purpose logic family and demonstrated a CMOS static memory. (computerhistory.org)

Early high-volume uses included digital watches and portable instruments, where battery life mattered more than maximum speed. Improvements in lithography and silicon-gate processing later made CMOS competitive in performance. As increasing transistor density created greater power-density problems, CMOS’s low steady-state consumption became increasingly valuable for large-scale integration and microprocessors. (computerhistory.org)

The technology’s development has included both shrinking dimensions and changing materials. Intel’s 2007 introduction of high-k dielectrics and metal gates in its 45-nanometer process was one documented milestone in reducing gate leakage while maintaining transistor performance. Such changes illustrate why CMOS denotes a continuing device-and-circuit family rather than a fixed historical fabrication recipe. (timeline.intel.com)

Analog, radio-frequency, and imaging applications

The term CMOS is broader than complementary digital logic. A CMOS manufacturing process can support analog and mixed-signal circuits, including amplifiers, converters, and radio-frequency circuitry. Such designs may require additional passive components and specialized device options. Optimizing a process for digital switching does not automatically optimize it for analog gain, matching, or radio-frequency behavior. (intel.com)

A CMOS image sensor combines light-sensitive elements with electronic readout circuitry fabricated using CMOS-compatible technology. In an active-pixel sensor, pixels contain active circuitry that assists signal readout. Work at NASA’s Jet Propulsion Laboratory in the 1990s contributed to CMOS active-pixel technology subsequently used in camera phones, webcams, digital cameras, and medical imaging. “CMOS sensor” names this application of the technology, not a synonym for CMOS as a whole. (ntrs.nasa.gov)

Limitations and reliability

CMOS circuits have finite switching speed because transistor current must change voltages on capacitive nodes. Increasing a gate’s output load increases the charge it must move, affecting delay and power. Inputs that remain at intermediate voltages can also leave both sides of an input stage partly conducting, increasing consumption. (ocw.mit.edu)

Conventional bulk CMOS structures can be susceptible to latch-up. Adjacent doped regions form parasitic bipolar transistors that can act together as a thyristor. If triggered, this structure creates a sustained, low-resistance path between supply rails, potentially disrupting operation or damaging the device. Layout, well contacts, isolation, and protection structures influence susceptibility. (ti.com)

Electrostatic discharge can damage thin insulating layers or junctions, so CMOS devices incorporate protection circuitry. Protection does not imply immunity to arbitrary electrical stress. Moreover, low standby power in digital logic does not guarantee low consumption for an entire CMOS chip: analog bias circuits, continuously active functions, switching loads, and leakage must all be included in its power budget. (ti.com)

References

1. 1963: Complementary MOS Circuit Configuration is Inventedcomputerhistory.org
2. CMOS Power Consumptionti.com
3. High-k and Metal Gate Transistor Researchintel.com
4. Computation Structuresocw.mit.edu
5. MITOCW: MOSFETs and CMOSocw.mit.edu
6. 1 Annotated Slides: Combinational Logicocw.mit.edu
7. Combinational Logic Lecture Slidesocw.mit.edu
8. Selecting the Correct Texas Instruments Signal Switchti.com
9. Micro/Nano Processing Technology: Lecture 18ocw.mit.edu
10. SRAM Cell: Computation Structures Lecture Slidesshd.mit.edu
11. Latch-Up, ESD, and Other Phenomenati.com
12. Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutionsdoi.org