{
  "id": "graphics-card",
  "title": "Graphics Card",
  "lang": "en",
  "source_lang": "en",
  "summary": "A circuit board built around a GPU, with memory, power circuitry, cooling and connectors, used to render images and run parallel computing workloads.",
  "category": "computer-science",
  "subcategory": "hardware",
  "type": "concept",
  "aliases": [
    "video card",
    "display adapter",
    "graphics adapter",
    "add-in board (AIB)"
  ],
  "generated_at": "2026-10-07",
  "model": "pro/claude-haiku-5-5",
  "url": "https://aiwiki.page/en/graphics-card/",
  "translations": {
    "zh-Hans": {
      "url": "https://aiwiki.page/zh/graphics-card/",
      "json": "https://aiwiki.page/zh/graphics-card.json"
    }
  },
  "sections": [
    {
      "heading": "",
      "text": "A graphics card (also called a video card, display adapter or graphics adapter) is a circuit board that carries a GPU, its own memory, power-delivery circuitry, cooling hardware and connectors, so that a computer can generate images for one or more displays. The GPU is the processor chip at the center of the card, and the card is the complete product that plugs into a computer's expansion slot. The distinction matters because the same GPU design can appear on boards with very different memory sizes, cooling systems and power budgets, and because many computers now use GPUs that are built into the main processor package rather than on a separate board.\n\nGraphics cards matter because the rendering task they were designed for, computing the color of millions of pixels many times per second, is highly parallel. Their design, built on many small processing units working together, has made them central to video games, film and visualization, scientific simulation and, since the late 2000s, machine-learning and artificial-intelligence. This shift has turned a niche consumer component into one of the most valuable classes of processor in the computing industry.\n\nThis entry first describes the physical components of a card and the rendering pipeline it implements, then explains the parallel architecture that makes GPUs efficient. It traces the history from early display adapters to programmable shaders and general-purpose computing, and discusses the software ecosystems that let programmers use GPUs. It then covers deep-learning accelerators, applications beyond graphics, the structure of the industry, the economics of supply and demand, and the energy and cooling challenges of high-performance cards."
    },
    {
      "heading": "Hardware Components and Form Factors",
      "text": "Anatomy of a card\n\nA graphics card is a printed circuit board (PCB) that carries the GPU die, the memory, the power circuitry, a cooler and the connectors. The die is the silicon part that performs the arithmetic, and the part of the GPU that performs the mathematical operations is called the \"die\". The memory on the board is video memory, which stores textures, frame buffers, and models. Consumer cards usually use GDDR chips placed around the die, while high-end and data-center designs use HBM, in which memory dies are stacked vertically and connected to the processor via an extremely wide interface on an interposer.\n\nThe voltage regulator module (VRM) is the power-conversion stage. It generally converts 12V to around 1V to 1.5V, which is close to the operating voltage of the chip. It is built from MOSFETs, inductors and capacitors, and because these parts run hot, they need their own heatsinks. Capacitors and inductors also filter and smooth the electrical current before it reaches the GPU.\n\nThe cooler is typically a heatsink with fans, heat pipes or liquid cooling. In hybrid designs, a liquid loop cools the die while a heatsink and fan handle the memory and VRM. Thermal pads move heat away from the GDDR memory, while thermal paste transfers heat from the GPU die to the large copper heatsink.\n\nThe card connects to the host through a PCIe edge connector, which is a gold-plated connector linking the card to the motherboard. Larger cards also need auxiliary power connectors. Outputs include HDMI and DisplayPort ports.\n\nMemory capacity, bus width and bandwidth\n\nCapacity and bandwidth are different properties. Capacity decides how much data fits on the card. Bandwidth decides how quickly the GPU can read and write that data, which matters when large textures or datasets are streamed in every frame. Bandwidth can be estimated with the formula\n\n\\[B = \\frac{W \\times r}{8}\\]\n\nwhere \\(W\\) is the bus width in bits, \\(r\\) is the effective per-pin data rate in Gbit/s, and \\(B\\) is in GB/s. Some calculators include an extra factor of 2 when they start from the memory clock instead of the effective rate, so the input convention must be checked. Take a card with a 256-bit bus and GDDR6 memory at an effective 14 Gbps; this means it can transfer up to 448 gigabytes of data per second. A 384-bit bus at 21 Gbps yields about 1008 GB/s, as in the RTX 4090 preset.\n\nBus width is where HBM differs. Its very wide interface runs at lower clock speeds and lower power than GDDR achieving similar bandwidth. A single HBM stack carries a 1024-bit interface, so a card with four stacks would have a 4096-bit memory bus.\n\nCapacity guidance for games is usually framed by resolution. One vendor-oriented guide suggests 8 GB is sufficient for 1080p, 12 GB for 1440p, and 16 GB+ for 4K. When a working set exceeds the local memory, data must cross the slower PCIe link, which reduces performance.\n\nDiscrete cards and integrated GPUs\n\nA discrete card is a separate board. In the words of one overview, discrete graphics cards are independent hardware units that have both a graphics processor and VRAM. These cards are mounted via the PCIe slots and have special power connectors.\n\nAn integrated GPU is built into the same package as the CPU or onto the same chip. It has no dedicated memory pool and instead uses the system's main RAM, which is shared with the CPU. This lowers cost, power and board complexity, but the GPU competes with the CPU for bandwidth. Many personal computers and laptops include both an integrated GPU and a discrete one, switching between them according to workload.\n\nForm factors\n\nDesktop cards are full-length PCIe boards, often occupying two or more expansion slots, and they carry their own cooling. Laptops have historically used a different approach. The Mobile PCI Express Module (MXM) is an interconnect standard for GPUs in laptops, created by the MXM-SIG, and its aim was a non-proprietary, industry standard socket, so one could easily upgrade the graphics processor in a laptop. In practice, most post-2017 laptops eliminated them entirely in favor of BGA-soldered GPUs.\n\nWorkstations generally use PCIe cards with more robust cooling and certified drivers. Servers and data centers use PCIe accelerators in standard slots, as well as socketed modules and board-mounted accelerators, which are mounted directly on a baseboard and linked to neighbouring units with high-speed interconnects. These modules trade the familiar card shape for higher power limits and direct liquid or dense air cooling.\n\nPower and heat as design constraints\n\nThe chip sets the performance ceiling, but the board determines whether that performance can be sustained. A large die packs in many transistors and draws considerable electric energy, so the resulting heat load is severe. Designers must deliver clean, stable current to the die and memory, which shapes the placement of the VRM, the number of layers in the PCB and the choice of connectors. They must also remove the heat quickly enough to avoid throttling. An effective cooling system enhances performance, increases the life of parts and will not be affected by thermal throttling during heavy workloads. For this reason, a graphics card is best understood as a complete thermal and electrical system built around the chip, not as the chip alone."
    },
    {
      "heading": "Rendering Pipeline and Fixed-Function Stages",
      "text": "From application to frame buffer\n\nReal-time rendering on a graphics card runs as a pipeline. The application on the CPU prepares vertex data such as positions, normals and texture coordinates, uploads textures and shader programs to video memory, and submits draw commands through a graphics API. The GPU then processes those commands in a fixed sequence of stages: vertex processing, primitive assembly, rasterization, fragment (pixel) shading and output merging. Early hardware implemented most of these stages as fixed-function circuits with configurable parameters. From the early 2000s, the vertex and fragment stages became programmable, but the overall order has stayed largely the same.\n\nVertex processing transforms each vertex from model coordinates into screen-related coordinates by multiplying it with transformation matrices and computing per-vertex quantities such as lighting. Primitive assembly groups the transformed vertices into triangles, clips the parts that fall outside the view volume, and removes triangles that face away from the camera. The GPU then divides by depth to apply perspective and maps the result onto the viewport, so each triangle has a position in pixel space. Rasterization decides which pixels each triangle covers and interpolates attributes such as depth, color and texture coordinates across the triangle, usually with barycentric weights. Each covered pixel produces a fragment, a candidate for the final color.\n\nFragment shading computes a color for every fragment, typically by sampling textures and evaluating lighting. Output merging then decides whether each fragment survives and how it combines with what is already stored. Depth tests, stencil tests and alpha blending run here, and the result is written into the frame buffer. Dedicated raster operations units perform these final steps. Because thousands of triangles and millions of fragments are processed for each frame, the GPU's job is essentially to convert a stream of geometry into a grid of colored pixels as fast as possible.\n\nFixed-function operations\n\nSome operations remain in dedicated hardware because they are repetitive and performance-critical. Texture mapping assigns image data to surfaces by converting interpolated texture coordinates into texel addresses and then filtering the samples. Filtering modes range from nearest-neighbor and bilinear sampling to trilinear and anisotropic filtering, which reduce blurring and aliasing at oblique viewing angles. Mipmaps, which store pre-filtered lower-resolution copies of a texture, reduce aliasing and the memory bandwidth needed to fetch texels. Texture units handle addressing, filtering and often decompression in hardware, so shader cores do not have to spend cycles on these tasks.\n\nZ-buffering, or depth buffering, stores a depth value for each pixel. When a new fragment arrives, the hardware compares its depth with the stored value and keeps it only if it is closer to the viewer. Modern GPUs perform this test early, before fragment shading, whenever a shader does not change depth, so hidden fragments are discarded without wasted computation. Frame buffering, in turn, keeps at least one off-screen buffer for drawing while another is shown on the display. Double buffering swaps the two buffers at a chosen moment, usually synchronized with the display refresh, which prevents the tearing that occurs when a partly drawn image is shown. Triple buffering adds a third buffer to smooth frame pacing at the cost of some extra latency.\n\nRasterization and ray tracing\n\nRasterization is the dominant method in real-time rendering because it projects geometry onto the screen and processes each primitive independently, which maps well onto parallel hardware. Its cost grows roughly with the number of triangles and covered pixels. Effects such as shadows, reflections and indirect light are usually approximated with extra passes, precomputed data or screen-space tricks. Ray tracing takes the opposite approach. It casts rays from the camera through each pixel, finds the nearest intersection with the scene, and may cast secondary rays toward light sources or reflective surfaces. Acceleration structures such as bounding volume hierarchies keep these intersection searches manageable.\n\nPath tracing extends ray tracing to follow light through many bounces and integrates the contributions with Monte Carlo sampling, which yields physically based global illumination. Because each pixel needs many samples to converge, path-traced images are expensive to compute, and real-time or near-real-time systems usually combine a few samples per pixel with denoising. This cost is the reason rasterization remained the default for interactive graphics for decades.\n\nHardware ray-tracing units were added to GPUs to accelerate the core operations of ray tracing, especially traversing acceleration structures and testing rays against triangles. NVIDIA introduced such units, which it called RT cores, with its Turing architecture in 2018. AMD added ray accelerators with RDNA 2 in 2020, and Intel included ray-tracing units in its Arc graphics processors in 2022. Before these units existed, the same intersection tests ran on general shader cores, which made them much slower. Most games today use hybrid rendering, in which rasterization handles primary visibility and ray tracing is applied selectively to reflections, shadows or global illumination."
    },
    {
      "heading": "Parallel Architecture of the GPU",
      "text": "A GPU is built on a different bargain from a CPU. A CPU spends its silicon on a few large cores with deep control logic and big caches, so that each task finishes quickly. A GPU fills its die with thousands of small, simple cores and accepts that each one is slow. Sources describe this as trading latency for throughput: a GPU trades latency for volume. The payoff comes only on data-parallel work, where one operation repeats across huge arrays. Code full of branches or steps that depend on earlier results leaves most of those cores idle, which is why CPUs remain better suited to that kind of logic.\n\nWarps, SIMT and Streaming Multiprocessors\n\nThe cores are grouped into streaming multiprocessors (SMs), and each SM schedules threads in fixed bundles. In NVIDIA's design the bundle, called a warp, usually holds 32 threads. In normal execution, all threads of a warp execute the same instruction in parallel, a model usually labelled SIMT, or single-instruction, multiple-thread. SIMT is best understood as a programming abstraction layered over SIMD hardware. The hardware issues one instruction per warp, and its execution lanes process it across the threads together. SIMT therefore did not replace SIMD. Instead, it reorganized the abstraction around threads while preserving SIMD efficiency underneath.\n\nThe model breaks down when threads disagree about control flow. If some threads in a warp take an if branch and others do not, the hardware runs one path with the non-matching threads masked off, then runs the other path with the complementary set. Each thread keeps its own program state, but the serialized paths cost time. When the threads in a warp split from one another to execute different instructions, also known as warp divergence, performance generally drops precipitously. Programmers therefore try to keep neighbouring threads on the same path.\n\nThe Memory Hierarchy and Its Bandwidth Limits\n\nMemory is organized in tiers that trade capacity for speed. At the top, each thread has a logically private set of registers, meaning other threads cannot access them. Registers are limited: a thread receives only a few of them, and values that do not fit are pushed out. If a thread block needs more registers than available, register values spill over to global memory.\n\nNext is shared memory, a programmer-managed scratchpad on each SM. Fast on-chip memory shared among different threads in a single block, but not between blocks. It is far faster than off-chip memory but much smaller. One study notes that shared memory has an order of magnitude higher bandwidth than global memory but has much smaller capacity (a few MB vs. multiple GB). The L1 cache sits beside it on each SM, and the L2 cache is shared by all SMs. L2 cache is the largest on-chip memory, shared by all SMs on the GPU, and acts as the last fast stop before going to HBM.\n\nGlobal memory is the slowest tier, and the bandwidth figures show why it matters. The global memory is the slowest but largest memory component on a GPU device with latency around 1000 cycles if TLB miss or 350 cycles if TLB hit. Bandwidth is also finite. One comparison of an A100 notes that its compute units can reach hundreds of teraFLOPS, yet its global memory bandwidth is limited to roughly 1.5 - 2 TB/s. Kernels must therefore reuse data in shared memory and registers, or the arithmetic units stall waiting for operands.\n\nScheduling and Latency Hiding\n\nBecause global memory latency is so high, a GPU does not try to shorten it. It hides it. Each SM keeps many warps resident at once, and its scheduler picks a warp whose operands are ready on each cycle. When one warp issues a load and must wait hundreds of cycles, the scheduler switches to another warp, and the switch costs little because each warp's register state stays on chip. A CPU takes the opposite approach and relies on large caches to avoid waiting. While a CPU relies heavily on its cache layers to maintain low latency, a GPU dedicates most of its transistors to computation rather than caching, allowing it to handle parallel computations even when there is a delay in retrieving data from memory. Enough resident warps keep the arithmetic units busy during these waits, although a kernel with too little parallelism or too many registers per thread cannot fill the SM.\n\nSpecialized Units Inside the Chip\n\nAlongside the general-purpose cores, each SM contains fixed-function hardware. Load/store units handle memory requests, and special function units evaluate operations such as reciprocals and trigonometric functions. Texture units, which perform filtered sampling of image data, are a legacy of graphics work and remain on the chip for compute workloads that use texture memory.\n\nThe most important addition for machine learning is the tensor core. Tensor Cores accelerate these multiplications using mixed precision, dramatically reducing training time. A tensor core multiplies small matrix tiles in a single operation, which is far more efficient than issuing the same products one at a time on ordinary cores. Ray-tracing units, which accelerate ray–scene intersection tests, are another example of fixed-function logic placed beside the shader cores, and they are discussed in the rendering section."
    },
    {
      "heading": "Origins: From Display Adapters to 3D Accelerators (1981–1999)",
      "text": "Graphics hardware in the personal computer began as a simple display device. In 1981 IBM offered the Monochrome Display Adapter (MDA), which was built for sharp text on a dedicated monitor, and the Color Graphics Adapter (CGA), the company's first colour card for the IBM PC. CGA's colour and resolution were modest even for its time, yet it became a de facto display standard. MDA proved more popular in business settings, where text mattered more than colour. The Enhanced Graphics Adapter (1984) superseded CGA, and the Video Graphics Array (VGA) introduced in 1987 set the resolution and colour expectations that PC software and monitors were designed around for years.\n\nThrough the early 1990s, these boards did little beyond the display itself. Their main job was to hold a frame buffer, the memory that stores the image sent to the screen, and to draw simple shapes when the processor asked. Almost all of the computation happened on the CPU. The CPU transformed geometry, rasterized triangles into pixels, and filled textures. Games such as Doom and, later, Quake were rendered entirely in software on the processor, and Quake was among the first to depend on a floating-point unit. Hardware acceleration therefore meant offloading specific steps from the processor, not replacing the rendering process.\n\nThe 3dfx Voodoo, released in 1996, was the first widely adopted consumer 3D accelerator. Its SST1 architecture was built from two specialized, non-programmable chips with separate memory. The frame buffer interface chip handled depth (z-buffer) tests, blending and the colour and depth buffers, while the texture mapping unit applied bilinear and trilinear filtering to textures held in its own memory. The CPU still performed the vertex work: it multiplied matrices, culled and clipped triangles, and then sent screen-space triangles to the card over the PCI bus. The Voodoo's rendering quality and speed made it the benchmark that rival products were judged against. Its proprietary Glide interface also meant that many early 3D games shipped separate versions for 3dfx hardware.\n\nNVIDIA's GeForce 256, announced on 31 August 1999 and released on 11 October 1999, moved transform and lighting (T&L) onto the graphics chip itself. Transform and lighting, the calculations that position polygons relative to the camera and determine how light falls on them, had previously been run by the CPU or by costly professional boards. NVIDIA described the product as a single-chip processor with integrated transform, lighting, triangle setup and rendering engines, and it marketed the chip as the first \"GPU.\" The term had earlier precedents: in 1997, 3Dlabs had used \"geometry processor unit\" for its programmable Glint Gamma T&L engine, and sources differ on how much weight the label deserves, since NVIDIA's distinction was largely a matter of marketing. The GeForce 256 used four pixel pipelines, was fully compatible with Direct3D 7, and later received a DDR-memory version.\n\nThroughout this period, competition among vendors such as 3dfx, NVIDIA and ATI pushed the industry away from proprietary interfaces. Developers increasingly targeted standard application programming interfaces (APIs), in particular Direct3D within Microsoft's DirectX and OpenGL, rather than writing for each card's own library. Hardware T&L itself was an example of this shift, since it was adopted as a feature of the Direct3D pipeline. By the end of the decade, a card's value depended less on a vendor's private software and more on how well it executed the standard pipeline, which set the stage for the programmable shaders of the next period."
    },
    {
      "heading": "Programmable Shaders and Unified Architectures (2000–2008)",
      "text": "Before 2001, the stages that transformed vertices and colored pixels on a consumer card were fixed circuits. Software could select among their built-in options but could not change the calculations themselves. The shift began with the GPU generation that Nvidia launched in early 2001. Launched in February 2001, the GeForce3 (NV20) introduced programmable vertex and pixel shaders to the GeForce family and to consumer-level graphics accelerators. Each chip contained one vertex unit and four parallel pixel units, and developers could load small programs into them. When enabled, these shader programs replace the corresponding fixed-function stage of the pipeline. The standard behind this was Microsoft's DirectX 8.0, which introduced Shader Model 1.0, which specified programmable vertex and pixel shaders—code that developers could write to control exactly how geometry was transformed and how each pixel's final color was computed.\n\nThe two units were used for different purposes. The vertex side let applications move geometry work off the CPU: it allows developers to manipulate geometry on the video card rather than the CPU. Examples included deformations such as facial animation or skinning; lighting, shading, bump mapping; and even motion blur and realistic fur. The pixel side handled surface appearance, supporting a wide variety of effects, including realistic shadows and reflective bump maps. Nvidia's marketing at the time stressed materials and surfaces that mimic reality. Early demonstrations, such as real-time renderings of Pixar's Junior Lamp and id Software's Doom 3 at the 2001 Macworld event in Tokyo, showed what the new hardware could do. The GeForce 3 also added multisample anti-aliasing and improved the overall efficiency of the rendering process.\n\nSeparate vertex and pixel hardware had structural drawbacks. Vertex shaders usually needed far more instructions than pixel shaders, so a fixed split of hardware between the two stages was costly in its own way: sometimes leaving one set of shaders idle if the workload used one more than the other. As fabrication improved, the distinction mattered less, and designers moved toward a unified shader model. In a unified design, one pool of shader processors can run any program type, so the GPU can reassign its capacity to the current workload. In a situation with a heavy geometry workload, the system could allocate most computing units to run vertex shaders and geometry shaders. In cases with a lighter vertex workload and a heavier pixel workload, more computing units could be allocated to run pixel shaders.\n\nThe first commercial unified design came from ATI rather than Nvidia. ATI Technologies introduced a unified architecture on the hardware they developed for the Xbox 360. Nvidia quickly followed with their Tesla design. Nvidia's GeForce 8800 GTX, released on November 8, 2006 and based on the G80 chip, was marketed as the industry's first fully unified architecture-based DirectX 10–compatible GPU. It used a massively parallel, unified shader design consisting of 128 individual stream processors running at 1.35 GHz. Each processor is capable of being dynamically allocated to vertex, pixel, geometry, or physics operations. The architecture also changed the instruction set that the hardware executed. Tesla's stream processors were a homogeneous collection of universal floating point processors rather than separate pixel and vertex units. AMD followed with its own unified PC design, the R600 family, in 2007. Accounts differ on the exact order of first availability for PC hardware, so claims of \"first\" should be read against the specific product and API.\n\nDirect3D 10 also codified the change. It introduced geometry shaders, a third programmable stage, and shaders across the pipeline were governed by one common model. Programmability then produced a wider range of visual effects, including more convincing lighting, surface materials, and screen-space post-processing applied after the scene is rendered.\n\nThe same flexibility also widened the gap between what graphics workloads needed and what the hardware could do. Shader units built for lighting arithmetic and texture operations were, after unification, a large array of floating-point processors that could be assigned to other computation. Developers who wanted to run simulations or other non-graphics code had to disguise their work as shader programs. This pressure led to the general-purpose computing efforts that followed, including CUDA in 2007."
    },
    {
      "heading": "GPGPU and Programming Ecosystems",
      "text": "From shaders to general-purpose computing\n\nGPUs were first programmed through graphics interfaces. Before programmable pipelines existed, scientists who wanted to use graphics hardware had to learn the rendering pipeline in detail and recast their problems as drawing operations, which limited adoption. After programmable shaders arrived in the early 2000s, researchers found that the same hardware could accelerate linear algebra, matrix-matrix multiplication, linear solvers, fluid-flow solvers and molecular dynamics. A common early technique was \"ping-pong\" rendering, in which two textures alternately served as read and write targets, so that the output of one shader pass became the input of the next. The shading languages that made this possible grew from Stanford's real-time shading language, which led to NVIDIA's Cg, and then to Microsoft's HLSL and OpenGL's GLSL. The Brook project, which extended C with GPU declarations to hide shader complexity, became a direct predecessor of NVIDIA's later platform.\n\nCUDA and its programming model\n\nNVIDIA's CUDA platform was announced in November 2006 and released in 2007, and it let programmers write C or C++ code with extensions for parallel kernels and explicit device memory management, bypassing graphics APIs entirely. A kernel is a function launched by the host CPU and executed by many threads, each of which uses built-in index variables to select its own data. Threads are organized into blocks, and blocks form a grid. On current GPUs a block may contain up to 1024 threads, and all threads of a block run on the same streaming multiprocessor, which constrains how many resources they can share. Threads in a block can cooperate through shared memory that lives as long as the block, and they can synchronize with a barrier call so that no thread proceeds until all have arrived. Each thread also has private local storage, and all threads can reach global device memory. The hardware executes threads in groups of 32, called warps, which is a detail programmers must consider when they tune performance.\n\nOpen alternatives and portability\n\nThe main competitor to CUDA's proprietary model is OpenCL, an open standard for parallel programming across GPUs, CPUs and other accelerators. Vulkan, maintained by the Khronos Group, offers compute shaders written in GLSL or HLSL and compiled to the SPIR-V intermediate representation. It runs on hardware from NVIDIA, AMD, Intel and mobile vendors, but it gives less direct access to vendor-specific matrix units. AMD's ROCm platform, first released in 2016, supports HIP, a C++ dialect whose syntax closely mirrors CUDA, and AMD supplies a tool that translates CUDA source into HIP. Portability is nevertheless incomplete. Source code can often be moved with modest changes, but performance usually depends on architecture-specific tuning, and some analysts consider OpenCL poorly suited to modern AI workloads. Translation projects such as clspv and clvk have tried to run OpenCL on top of Vulkan.\n\nLibraries, compilers and software maturity\n\nMost scientists never write kernels themselves. They rely on libraries that wrap common operations: BLAS routines such as cuBLAS on NVIDIA hardware and rocBLAS on AMD hardware, the hipBLAS layer that dispatches to either, and fast Fourier transform and dense solver libraries such as rocFFT and rocSOLVER. Deep learning frameworks sit on top of similar stacks, which is why a single high-level API can target different vendors. Beneath these libraries, compiler and driver layers translate high-level code into device instructions. ROCm, for instance, builds HIP, OpenMP and OpenCL on a common driver stack, while SPIR-V serves as a portable intermediate form that can be lowered to a particular vendor's instruction set. Software maturity is often decisive. Commentators in 2026 generally regard CUDA as the de facto standard for AI and machine learning, arguing that its toolchain and library depth are a real performance advantage, while acknowledging that ROCm has narrowed the gap. For many developers, the cost of this ecosystem lock-in is weighed against the performance and tooling of the vendor's own platform."
    },
    {
      "heading": "Deep Learning and Data-Center Accelerators",
      "text": "Why neural networks suit GPUs\n\nMost of the arithmetic in a neural network reduces to large matrix multiplications, and many of the products in each layer are independent of one another. That structure fits the wide parallelism of GPUs, which is why they became the standard hardware for training deep learning models from the early 2010s. Vendors then added dedicated units for the matrix work. Tensor cores are specialized hardware units in NVIDIA GPUs that accelerate matrix multiply-accumulate operations. Unlike traditional cores, they process entire matrix tiles in parallel. Data-center chips such as the A100, H100 and B200 generations are built around these engines for deep learning, which is why their design emphasis differs from that of gaming cards. NVIDIA's data center GPUs, such as the A100 (Ampere), H100 (Hopper) and B200 (Blackwell), are built for deep learning, utilizing Tensor Cores that execute matrix multiply-accumulate operations.\n\nLow-precision formats and throughput\n\nLower-precision number formats trade numerical accuracy for speed and memory savings, and the choice of format is a central design decision. FP16 has 1 sign bit, 5 exponent bits and 10 mantissa bits, and its narrow exponent range makes overflow a practical risk. BF16 has 1 sign bit, 8 exponent bits and 7 mantissa bits, so its range matches FP32 and it is generally more stable for training. BF16 is safer than FP16 in practice because it mirrors FP32's exponent range: overflow is extremely rare. FP8 is more aggressive and comes in two variants, E5M2 and E4M3, which offer flexibility in dynamic range versus precision trade-offs.\n\nThe gains are substantial. An NVIDIA A100 can achieve around 312 teraFLOPs in FP16/BF16 compute via Tensor Cores, versus ~19.5 teraFLOPs in standard FP32. Support has grown generation by generation: the A100 introduced the TF32 format and enhanced support for FP16 and BF16, while the H100 added FP8 via its Transformer Engine. That engine performs matrix multiplications in FP8 while accumulating results at higher precision. FP8 training is harder to get right. Its results can depend on careful scaling and hyperparameter tuning, so practitioners often keep master weights and sensitive layers in higher precision.\n\nMemory bandwidth and interconnects\n\nData-center accelerators pair their compute with very fast memory. Their high-bandwidth memory stacks sit on the package; the H100 SXM is listed at 3.35 TB/s, and the B200 pairs 192 GB of HBM3e memory and 8 TB/s bandwidth. Bandwidth matters most once many GPUs must exchange gradients and activations. NVLink is a proprietary interconnect for NVIDIA GPUs, and its design addresses the bandwidth limits of PCIe, which has been observed to be a transfer bottleneck in GPU-accelerated applications. For comparison, a typical PCIe 5.0 x16 slot provides 128 GB/s of bidirectional bandwidth. Fourth-generation NVLink provides 900 GB/s of GPU-to-GPU interconnect bandwidth per H100 accelerator. The Blackwell generation raises this further, to 1.8TB/s bidirectional throughput per GPU, providing high-speed communication among up to 576 GPUs.\n\nLarge clusters therefore use layers of connectivity. NVLink handles traffic inside a server, while network fabrics handle traffic between servers. InfiniBand with RDMA provides a fast, low-latency network for connecting multiple servers into a large, cohesive training cluster. NVLink is not fully uniform, either: if two GPUs do not have a direct NVLink connection, communication has to be routed through an intermediate GPU.\n\nTraining versus inference\n\nTraining and inference place different demands on the same hardware. Training runs repeated forward and backward passes over a full dataset, sometimes for days. The GPU must sustain peak FLOP throughput across the entire run, and VRAM must simultaneously hold model parameters, gradients, Adam optimizer states, and intermediate activations. Inference is a different workload. Inference runs a single forward pass per request. The GPU must minimize time-to-first-token and sustain tokens-per-second across concurrent requests. Because weights are reloaded on every pass, transfer speed determines actual throughput more than tensor core multiply rates. As a result, inference-optimized configurations, with smaller VRAM, lower power draw, and sometimes lower-precision support like FP8 or INT8, often deliver better cost per request even though their peak FLOPS are lower. The boundary is blurring as reasoning models generate more output, so inference is no longer always the light workload.\n\nServer accelerators and consumer cards\n\nServer accelerators differ from consumer graphics cards in more than raw speed. A single model can come in several variants: variations exist in the intra-node connections between A100 GPUs (SXM versus PCIe), depending on resource constraints and system usage. SXM modules are designed to be seated on a server's baseboard and linked through NVLink, whereas PCIe cards fit ordinary expansion slots. Rack-scale systems extend the same idea: NVIDIA's NVLink Switch domains can tie 72 GPUs into a single high-bandwidth \"island\". Data-center products also depend on enterprise drivers and a mature software stack, such as CUDA. Cooling and memory design are shaped by sustained operation in racks rather than by a single desktop enclosure."
    },
    {
      "heading": "Applications Beyond Graphics",
      "text": "The same features that suit a GPU to rendering, namely many simple cores, high memory bandwidth and the ability to apply one operation to large arrays of data, also suit many scientific workloads. These fields adopted GPUs as parallel computing became cheap enough to use outside graphics.\n\nIn scientific simulation, molecular dynamics (MD) advances the positions and velocities of atoms by repeatedly applying Newton's laws of motion, and the force calculations dominate the run time. Packages including AMBER, GROMACS, NAMD, OpenMM and LAMMPS now run these calculations on GPUs. Reported gains depend heavily on the code, the system and the baseline. A 2019 review noted that GROMACS ran about ten times faster on one older GPU than on a single CPU core, while AMBER exceeded fifty times because it kept both force evaluation and integration on the card, avoiding data transfers between GPU and host memory at every time step. Climate and weather models and astrophysical codes follow a similar pattern, since grid updates and pairwise gravitational interactions split naturally across thousands of threads.\n\nIn bioinformatics, the most visible example is protein structure prediction. Systems such as AlphaFold are deep neural networks whose computation consists largely of matrix operations, which is why they are trained and run on accelerators, including GPUs. Other tasks, such as sequence alignment, genomic analysis and molecular docking for drug screening, also have GPU implementations, although their speedups vary widely with problem size.\n\nMedical imaging is another long-standing use. In computed tomography, the raw projection data are large, and iterative reconstruction methods, which can reduce noise and artifacts, are computationally heavy; this cost slowed their clinical adoption. The back-projection and forward-projection steps at the core of these algorithms are highly parallel, so GPUs made them practical. A constraint remains: a card's video memory is much smaller than the host's system memory, so large volumes must be divided into blocks and processed piece by piece. In magnetic resonance imaging, a 2008 study by Stone and colleagues reported that GPU acceleration made an advanced reconstruction method practical for clinical use. On a Quadro-class GPU the reconstruction took minutes, and a quad-core CPU was about thirteen times slower; the advanced method also produced an error of about 12 percent, against 42 percent for conventional reconstruction.\n\nReal-time video and perception form a separate group. GPUs include dedicated fixed-function hardware for video encoding and decoding, and they handle real-time image processing such as filtering, denoising and upscaling. For robotics and driver-assistance systems, neural networks performing computer vision tasks such as object detection and segmentation run on embedded GPU modules, which must operate within tight power and thermal budgets. A 2025 preprint, for example, ran CT-to-MRI image generation and diagnostic detection concurrently on an NVIDIA edge module, reporting up to 170 frames per second, about twice the throughput of the original model.\n\nFilm and animation rendering is the most prominent offline use. Path tracing traces many light paths per pixel and is now the most common technique for photorealistic rendering, and it is widely used for animated features. Production renderers such as Sony's Arnold, used on the film Cloudy with a Chance of Meatballs, helped move most major computer-animated film productions to path-traced rendering. Because a real-time game can afford only a few rays per pixel, while a film frame may take minutes or hours with thousands of rays per pixel, offline renderers rely on GPUs for throughput rather than latency. Multi-GPU support in tools such as NVIDIA's Omniverse RTX renderer, which the vendor describes as achieving near-linear speedup on a single system with up to 16 GPUs, shortens render times further. Neural denoisers are often applied to reduce the noise left by low sample counts.\n\nSources\n\n- Accelerating Molecular Dynamics Simulations with GPUs (EasyChair preprint) | https://easychair.org/publications/preprint/GRjS/open\n- ddcMD: a fully GPU-accelerated molecular dynamics code (OSTI) | https://www.osti.gov/servlets/purl/1669229\n- MIST: A Simple and Efficient Molecular Dynamics Abstraction Library (arXiv) | https://arxiv.org/pdf/1805.07117\n- Accelerators for Classical Molecular Dynamics Simulations of Biomolecules (ACS) | https://pubs.acs.org/doi/10.1021/acs.jctc.1c01214\n- Parallel CT image reconstruction based on GPUs (ScienceDirect) | https://www.sciencedirect.com/science/article/abs/pii/S0969806X13001436\n- GPU-Based 3D Cone-Beam CT Image Reconstruction for Large Data Volume (PMC) | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC2734932/\n- Accelerating advanced MRI reconstructions on GPUs (ACM) | https://dl.acm.org/doi/10.1145/1366230.1366276\n- Edge GPU Aware Multiple AI Model Pipeline for Accelerated MRI Reconstruction and Analysis (arXiv) | https://arxiv.org/pdf/2510.01730\n- Real Time Cluster Path Tracing (arXiv) | https://arxiv.org/pdf/2110.08913\n- Rendering (computer graphics) (Wikipedia) | https://en.wikipedia.org/wiki/Rendering_(computer_graphics)\n- New NVIDIA Path Tracing Breakthrough Interactively Renders 7,000 Dynamic Lights (NVIDIA Developer Blog) | https://developer.nvidia.com/blog/turning-up-the-lights-interactive-path-tracing-scenes-from-a-short-film/\n- Omniverse RTX Renderer — Omniverse Materials and Rendering (NVIDIA Docs) | https://docs.omniverse.nvidia.com/materials-and-rendering/latest/rtx-renderer.html"
    },
    {
      "heading": "Industry Structure and Supply Chain",
      "text": "Discrete graphics is a concentrated market. Jon Peddie Research put NVIDIA at 90% of add-in-board shipments in Q1 2026, with AMD at 8% and Intel at 1%. In discrete consumer GPUs (add-in boards), Nvidia held 90% of shipments in Q1 2026 per Jon Peddie Research, with AMD at 8% and Intel at 1%. That measure covers standalone cards in desktop towers, so it excludes laptops and integrated chips. Other outlets report much higher AMD figures for desktop gaming, which shows how sensitive these shares are to the counting method. In desktop gaming, AMD holds roughly 15-20% market share globally as of early 2026.\n\nThe accelerator market for AI data centers is even more concentrated. Estimates for NVIDIA's share of 2026 AI accelerator revenue range from 75% to 81%, and one tally puts it at 87.4% of merchant AI data-center revenue in Q1 2026. AMD's share is smaller, and Intel's AI GPU share sits near 1%. Custom accelerators designed by hyperscalers such as Google and Amazon account for much of the remainder. NVIDIA, AMD and Intel also pursue different priorities: NVIDIA's revenue has shifted heavily toward data centers, while AMD competes in both gaming and server GPUs, and Intel is trying to build a semiconductor foundry business.\n\nMost leading designers are fabless. NVIDIA and AMD create their chip designs but send wafer production to outside contract manufacturers. TSMC is the world's largest semiconductor foundry, manufacturing chips designed by other companies (Nvidia, AMD, Apple, Broadcom) rather than selling chips under its own brand. As of Q1 2026, TSMC held approximately 73% of pure foundry market share by revenue, and an even greater share of advanced node manufacturing. Its lead rests on its 3nm and 2nm processes. Intel's manufacturing is different, since nearly all of the company's foundry demand comes from itself. The result is that a small number of firms can build chips at the newest nodes, so a single supplier's capacity decisions can affect the whole GPU industry.\n\nFabrication is only one bottleneck. Top AI accelerators depend on advanced packaging, especially TSMC's CoWoS, which combines logic dies and memory stacks on one substrate. Its most advanced method currently in use is called Chip on Wafer on Substrate, or CoWoS, and Rousseau said it is increasing at a stunning 80% compound annual growth rate. AI giant Nvidia has reserved a majority of the most advanced capacity available at TSMC, which is the volume leader in packaging. Estimates of the exact share vary, with one report saying Nvidia has secured roughly 60% of TSMC's advanced packaging capacity, while another describes NVIDIA locking up more than half of TSMC's advanced packaging capacity through 2027. Because packaging is so constrained, some observers argue that advanced packaging, not wafer fabrication, is now the binding constraint on AI accelerator production. TSMC has also sent some work to outside firms, and its Arizona advanced packaging facility is not expected to reach volume production before 2028, keeping supply tight until then.\n\nMemory is a second chokepoint, and the market for high-bandwidth memory (HBM) is shaped by a few suppliers. Contract rates for Hopper-class data-center GPUs reportedly rose sharply in late 2025 and early 2026, driven primarily by HBM3e memory cost pass-throughs from Samsung and SK Hynix rather than by GPU die shortages. Memory makers earn higher margins on HBM than on consumer graphics memory. When those companies prioritize wafer allocation toward HBM, which commands far higher margins, every other memory product, from a laptop's RAM to a graphics card's VRAM (video RAM) to a games console's system memory, becomes scarcer and more expensive. Relief is also slow, since new memory fabrication capacity from Micron and SK Hynix will not reach volume production until 2027 at the earliest. These pressures have fed into consumer prices: by the second quarter of 2026, GDDR7 memory prices had risen roughly 15% to 20% price increase reported by PC vendors, and the broader cost effects are discussed in the market and supply and demand sections.\n\nBoard partners sit between the designer and the buyer. They take the designer's reference board, add their own printed circuit boards, coolers and factory settings, and sell the finished cards under their own brands. Because memory is a large share of cost, graphics card makers and board partners are facing higher costs before the card even reaches store shelves. Software is the other competitive asset. The 2026 AI GPU market is characterized by NVIDIA's overwhelming revenue dominance, supported by its transition to a system-level provider and the unmatched maturity of the CUDA ecosystem. Developers who have built tools around CUDA face switching costs, and rivals must also match driver quality and game-side support. One analysis says driver maturity, ray-tracing optimization, and game-side software support remain AMD's primary market share constraints."
    },
    {
      "heading": "Market Cycles, Pricing and Demand",
      "text": "Gaming as the historical core\n\nFor most of its history, the GPU market rested on consumer gaming. Each product generation set a new launch price, and the models it replaced were then discounted. Tracking sites have observed that a successor's imminent launch pushes the current card onto the secondary market, where its price falls. Gaming's share of vendor revenue has since shrunk. In one analyst's account, gaming supplied 51% of NVIDIA's total sales in the second quarter of 2020, while data centers supplied 25%.\n\nMining booms and busts\n\nCryptocurrency mining added a second source of demand that was far less predictable than gaming. Analysts at Jon Peddie Research estimated that 25% of GPUs shipped in the first quarter of 2021 went to cryptocurrency miners and speculators. Scarcity pushed resale prices well above list prices. In January 2022, an RTX 3080 was reportedly resold for $1,613 against a retail price of $699.\n\nThe reversal was equally abrupt. Tom's Hardware reported a 15% price drop in May 2022, and similar monthly declines had been seen for several months before that. Ethereum's move to proof of stake then removed Ether mining from graphics cards altogether, and by the end of June 2022, before The Merge, graphics card prices had reportedly dropped by about 57% compared with January. Dedicated mining hardware did not protect vendors either. NVIDIA's CMP mining cards, which were meant to divert miners from gaming cards, saw revenue fall to negligible levels in 2022. The bust also reached gaming revenue. In the quarter ending in July 2022, NVIDIA's gaming revenue fell 33% from a year earlier, mainly because of lower sell-in to channel partners amid macroeconomic headwinds.\n\nThe data-center turn\n\nThe 2020s brought a structural change. A report on NVIDIA's most recent annual results put annual data-center revenue at $193.7 billion, while gaming brought in $16 billion over the full fiscal year, a 41% increase. In the latest quarter reported in one analysis, gaming produced just 5.5% of revenue above $68 billion.\n\nThis shift changed purchasing. Cloud providers and AI developers buy in volume, and vendors allocate scarce output accordingly. NVIDIA was reportedly considering output cuts of 30% to 40% for parts of its mid-range lineup, as it prioritised higher-margin products and AI accelerators. The company has also warned that GPU supplies would be limited in the first half of 2026 because of data-center commitments and global memory shortages. For the AI industry, the consumer card has become a secondary product whose supply depends on data-center priorities.\n\nPrice increases in 2026 and the memory shortage\n\nIn early 2026, NVIDIA and AMD were reportedly preparing phased price increases, driven mainly by video memory costs, with AMD expected to move first in January and NVIDIA to follow in February. The underlying cause was memory rather than GPU silicon. Demand for GDDR7, GDDR6 and high-bandwidth memory rose as AI data-center deployments expanded faster than supply could follow. Memory was reported to account for more than 80% of the bill of materials for some high-end cards. A contributing factor was that many GPU makers had fixed-price memory agreements through 2025, and those contracts have largely expired, with renewals at much higher prices.\n\nLater in the year, AMD informed partners that Radeon GPU and GDDR6 memory kit prices would rise by at least 10% starting in August. NVIDIA attributed its increases mainly to higher memory chip costs.\n\nThe forecasts and measured increases vary considerably, and the sources differ in method (list price, street price, or region):\n\n- A Tom's Hardware report put a floor of roughly 10% on the expected increases.\n- Supply-chain data reviewed in September 2026 suggested 15%–20% increases for RTX 50-series cards with 16GB or more of VRAM, and 10%–15% for broader AMD and NVIDIA memory-related increases.\n- Another estimate put price rises of roughly 19–20% globally since late 2025.\n- A European survey reported that NVIDIA GPU prices rose 41% and AMD prices 28% in three months.\n- At the extreme, NVIDIA's flagship GeForce RTX 5090 could reach prices as high as $5,000 later in 2026, according to the report.\n\nStreet prices illustrate the gap between list and retail. One source compares the RTX 5090 launch price of $1,999 in January 2025 with a July 2026 listing of $4,329 on Amazon, with some board-partner configurations exceeding $5,000. In June 2026, plaintiffs filed a federal antitrust lawsuit against Samsung, SK Hynix and Micron, alleging that the three companies coordinated to restrict DRAM supply. These allegations are unproven.\n\nResale and depreciation\n\nThe sources reviewed contained little reliable data on resale values for older data-center accelerators, so the general pattern below relies on consumer-card evidence. The usual mechanism is that a successor generation lowers the value of its predecessor. When supply is constrained, as in 2026, older hardware may hold value better, but this is an inference and not a documented trend in the material consulted."
    },
    {
      "heading": "Power, Cooling and Energy Efficiency",
      "text": "Board power and power delivery\n\nFor high-end cards, power is often the constraint that shapes the whole design. Manufacturers typically publish a total board power figure, an estimate of the maximum draw of the entire card under heavy load, covering the heat-producing GPU together with memory, voltage regulators and cooling fans. Flagship figures have climbed steadily. The RTX 5090 is rated at 575 watts TDP, and in 2026 flagship cards are commonly described as consuming 400-600 watts under full load. Ratings also understate brief peaks. One 2026 guide reports that a card rated at 220 W can briefly pull 350–400 W for a few milliseconds, which the power supply must absorb. The same cards also raise connector concerns; reviewers have flagged the 12V-2x6 connector and its cabling as under strain at 575 W.\n\nBecause of this, system builders size power supplies with generous margins. One common rule multiplies the combined draw of the CPU, GPU and other parts by a factor of roughly 1.2 to 1.3, and mid-to-high-end systems now commonly call for 750–1000 W units. Cards are also physically constrained by their enclosures: small form-factor cases often cap GPU power at about 200–250 W.\n\nCooling designs\n\nBoard designers remove the heat with three main approaches. Air coolers use a metal heatsink, usually with one to three fans; vapor chambers, which are sealed plates containing a working fluid, spread heat across the base of the heatsink more evenly than solid copper; and liquid cooling carries heat through a loop to a radiator, sometimes fitted with a large 360 mm unit. Each approach trades off noise, size and reliability. Air cooling is cheap and simple, but large fans can be loud and bulky. Liquid systems can run quieter and cooler at a given power, but add pumps, more parts that can fail and leakage risk, and they constrain case layout. When a card exceeds what its cooler or case can handle, it runs hotter, throttles under sustained load and drives its fans harder to compensate.\n\nPerformance per watt and efficiency metrics\n\nThe main efficiency measure is performance per watt, usually computed by dividing a benchmark score by measured power. Under this metric, the highest raw performance is not always the most efficient. In one 2026 chart normalized to the RTX 5090, a lower-TDP card with a fraction of that raw score can still rank ahead of it simply by drawing far less power. Efficiency improves through two channels. Process-node advances shrink transistors and reduce the energy each switching operation requires, while architecture changes alter how much work each unit of silicon does per cycle. Designers must balance both, because raising clock speeds to win benchmarks usually increases power faster than it increases performance.\n\nData-center energy demand\n\nEnergy concerns are now larger at the level of data centers than individual cards. Forecasts vary considerably. One summary of IEA projections puts global data-center consumption at 415 TWh in 2024, rising to 945 TWh by 2030, while Gartner's June 2026 forecast estimates 565 TWh of electricity in 2026, up 26.4% from 447 TWh in 2025. Within that total, AI-optimized servers are a fast-growing share. Rack density is rising sharply: AI-optimized GPU racks currently draw 40–80+ kW, and Nvidia's Blackwell racks were reported at roughly 120–130 kW. Per-query energy estimates also differ widely. One 2026 compilation cites a typical GPT-4o query uses roughly 0.3 watt-hours, far below older figures.\n\nOperators' concerns center on the availability and cost of electricity, grid connections and sustainability. An April 2026 market report estimated that about 7 GW of AI data center capacity had been delayed or cancelled because of power availability and grid queues. Cooling and power distribution add substantial overhead on top of IT load, and estimates of that overhead vary from roughly a third to 40 percent of facility electricity. Sustainability debates therefore focus on the emissions associated with that electricity and on how much of the grid capacity being added comes from low-carbon sources.\n\nReducing wasted computation\n\nSeveral techniques reduce the energy spent per useful result. Lower-precision arithmetic, which uses fewer bits per number (see floating-point-arithmetic), cuts the energy each operation requires, and sparsity methods skip multiplications involving zero-valued weights or activations. Upscaling is the most visible example in consumer graphics. The basic approach is to render the game at a lower internal resolution, then reconstruct a sharper, higher-resolution image before it hits your monitor. A 4K image rendered in a performance mode may involve only 1080p internal rendering, which is a quarter of the pixel workload. The reconstruction is performed by a neural network running on dedicated matrix hardware, such as the tensor cores in NVIDIA RTX cards. Upscaling is not free: a learned reconstruction step adds its own cost, and critics note that the technique can create blurry images. Vendors also limit the most aggressive modes; Nvidia recommends its Ultra Performance setting mainly for 8K output."
    }
  ],
  "links": [
    "graphics-processing-unit",
    "computer",
    "machine-learning",
    "artificial-intelligence",
    "personal-computer",
    "transistor",
    "electricity",
    "energy",
    "matrix",
    "monte-carlo-method",
    "ibm",
    "floating-point-arithmetic",
    "cuda",
    "shared-memory",
    "deep-learning",
    "parallel-computing",
    "alphafold",
    "x-ray-computed-tomography",
    "magnetic-resonance-imaging",
    "robotics",
    "computer-vision",
    "semiconductor",
    "market",
    "supply-and-demand",
    "data-center",
    "heat",
    "greenhouse-gas",
    "tensor"
  ],
  "sources": [
    {
      "title": "GPU (Hardware)",
      "url": "https://specfortech.wordpress.com/hardware/gpu-hardware/"
    },
    {
      "title": "What Does a Graphics Card Do? A Technical Guide to GPU Architecture and Rendering",
      "url": "https://www.origin-ic.com/blog/what-does-a-graphics-card-do-functions-components/49095"
    },
    {
      "title": "DDR, GDDR, and HBM Memory Speeds and Bandwidth",
      "url": "https://www.birow.com/ram-video-ram-sebessegei"
    },
    {
      "title": "Graphics Card Components & Connectors Explained",
      "url": "https://graphicscardhub.com/graphics-card-component-connectors/"
    },
    {
      "title": "What Is a Graphics Card? GPU Function, Components & Applications",
      "url": "https://www.blikai.com/blog/components-parts/what-is-a-graphics-card-gpu-function-components-applications"
    },
    {
      "title": "Graphics Card PCB Explained: Layers, Impedance, and BGA Assembly",
      "url": "https://www.pcbtok.com/graphics-card-pcb-explained/"
    },
    {
      "title": "Graphics card teardown: We dismembered a video card to show you how it works",
      "url": "https://www.pcworld.com/article/420096/graphics-card-dissection-we-dismembered-a-video-card-to-show-you-how-it-works.html"
    },
    {
      "title": "What is graphics memory bandwidth and why is it important",
      "url": "https://grafickekarty.sk/en/technologies/graphics-memory-bandwidth/"
    },
    {
      "title": "GPU Memory Bandwidth Calculator for Home Labs",
      "url": "https://thehomeserverblog.com/gpu-memory-bandwidth-calculator/"
    },
    {
      "title": "Mobile PCI Express Module",
      "url": "https://en.wikipedia.org/wiki/Mobile_PCI_Express_Module"
    },
    {
      "title": "MXM GPU Guide: How to Choose the Right Module for Edge or Upgrade",
      "url": "https://electronics.alibaba.com/buyingguides/mxm-gpu-guide-industrial-edge-vs.-legacy-laptop-use"
    },
    {
      "title": "Different Types of Graphics Card Cooling Solutions for GPU, VRAM & VRM",
      "url": "https://graphicscardhub.com/graphics-card-cooling-solutions/"
    },
    {
      "title": "High Bandwidth Memory",
      "url": "https://en.wikipedia.org/wiki/High_Bandwidth_Memory"
    },
    {
      "title": "GPU Bandwidth Calculator - Orbit6",
      "url": "https://www.orbit6.com/gpu-bandwidth-calculator/"
    },
    {
      "title": "CPU vs GPU: Key Differences and Use Cases",
      "url": "https://www.browserless.io/blog/cpu-vs-gpu"
    },
    {
      "title": "What is a Warp?",
      "url": "https://modal.com/gpu-glossary/device-software/warp"
    },
    {
      "title": "SIMD started it, SIMT improved it",
      "url": "https://www.jonpeddie.com/news/simd-started-it-simt-improved-it/"
    },
    {
      "title": "GPU memory hierarchy",
      "url": "https://handbook.modular.com/kernel-optimization/gpu-architecture-fundamentals/gpu-memory/"
    },
    {
      "title": "A Study of the Fundamental Performance Characteristics of GPUs and CPUs for Database Analytics (Extended Version)",
      "url": "https://arxiv.org/pdf/2003.01178"
    },
    {
      "title": "GPU Load Balancing",
      "url": "https://arxiv.org/pdf/2212.08964"
    },
    {
      "title": "CUTHERMO: Understanding GPU Memory Inefficiencies with Heat Map Profiling",
      "url": "https://arxiv.org/pdf/2507.18729"
    },
    {
      "title": "GPU Memory Hierarchy Mapping",
      "url": "https://apxml.com/courses/compiler-optimizations-machine-learning/chapter-5-hardware-aware-code-generation/gpu-memory-hierarchy-mapping"
    },
    {
      "title": "CPU vs GPU: What’s best for Machine Learning?",
      "url": "https://aerospike.com/blog/cpu-vs-gpu/"
    },
    {
      "title": "CPU vs GPU Accelerated Workloads. 1.0 Introduction",
      "url": "https://medium.com/@zbabar/cpu-vs-gpu-accelerated-workloads-7304ec9e7b99"
    },
    {
      "title": "SIMD Started It, SIMT Improved It - ACM SIGGRAPH Blog",
      "url": "https://blog.siggraph.org/2026/01/simd-started-it-simt-improved-it.html/"
    },
    {
      "title": "CPU vs GPU: How They Work and When to Use Them",
      "url": "https://www.datacamp.com/blog/cpu-vs-gpu"
    },
    {
      "title": "GeForce 256",
      "url": "https://en.wikipedia.org/wiki/GeForce_256"
    },
    {
      "title": "Nvidia’s GeForce 256: The First Fully Integrated GPU",
      "url": "https://www.electronicdesign.com/technologies/embedded/article/21178111/jon-peddie-research-nvidias-geforce-256-the-first-fully-integrated-gpu"
    },
    {
      "title": "Nvidia GeForce 256 celebrates its 25th birthday — company talks about a quarter century of GPU progression",
      "url": "https://www.tomshardware.com/pc-components/gpus/nvidia-geforce-256-celebrates-its-25th-birthday-company-talks-about-a-quarter-century-of-gpu-progression"
    },
    {
      "title": "Famous Graphics Chips: Nvidia’s GeForce 256",
      "url": "https://www.computer.org/publications/tech-news/chasing-pixels/nvidias-geforce-256"
    },
    {
      "title": "Retro Tech: Nvidia GeForce",
      "url": "https://www.raspberrypi.com/news/retro-tech-nvidia-geforce-custom-pc-223/"
    },
    {
      "title": "Color Graphics Adapter",
      "url": "https://en.wikipedia.org/wiki/Color_Graphics_Adapter"
    },
    {
      "title": "IBM Monochrome Display Adapter",
      "url": "https://en.wikipedia.org/wiki/IBM_Monochrome_Display_Adapter"
    },
    {
      "title": "Enhanced Graphics Adapter",
      "url": "https://en.wikipedia.org/wiki/Enhanced_Graphics_Adapter"
    },
    {
      "title": "Computer art scene",
      "url": "https://en.wikipedia.org/wiki/Computer_art_scene"
    },
    {
      "title": "The story of the 3dfx Voodoo1",
      "url": "https://fabiensanglard.net/3dfx_sst1/"
    },
    {
      "title": "3dfx Voodoo Graphics review",
      "url": "https://vintage3d.org/3dfx1.php"
    },
    {
      "title": "3Dfx’s Voodoo",
      "url": "https://www.electronicdesign.com/technologies/embedded-revolution/article/21131642/jon-peddie-research-3dfxs-voodoo"
    },
    {
      "title": "3dfx - Vogons Wiki",
      "url": "https://www.vogonswiki.com/index.php/3dfx"
    },
    {
      "title": "RIVA 128",
      "url": "https://en.wikipedia.org/wiki/RIVA_128"
    },
    {
      "title": "GeForce",
      "url": "https://en.wikipedia.org/wiki/GeForce"
    },
    {
      "title": "Benchmarking and Implementation of Probability-Based Simulations on Programmable Graphics Cards",
      "url": "https://arxiv.org/pdf/cs/0312006"
    },
    {
      "title": "Part I: The first fully programmable GPUs—a review",
      "url": "https://www.jonpeddie.com/news/part-i-the-first-fully-programmable-gpus-a-review/"
    },
    {
      "title": "GeForce3",
      "url": "https://www.cgw.com/Publications/CGW/2001/Volume-24-Issue-9-September-2001-/GeForce3.aspx"
    },
    {
      "title": "Nvidia Introduces GeForce3",
      "url": "https://www.gamedeveloper.com/game-platforms/nvidia-introduces-geforce3"
    },
    {
      "title": "GeForce 3 series",
      "url": "https://en.wikipedia.org/wiki/GeForce_3_series"
    },
    {
      "title": "Unified shader model",
      "url": "https://en.wikipedia.org/wiki/Unified_shader_model"
    },
    {
      "title": "NVIDIA GeForce 8800 Architecture Technical Brief",
      "url": "https://www.nvidia.co.uk/content/PDF/Geforce_8800/GeForce_8800_GPU_Architecture_Technical_Brief.pdf"
    },
    {
      "title": "Tesla (microarchitecture)",
      "url": "https://en.wikipedia.org/wiki/Tesla_(microarchitecture)"
    },
    {
      "title": "Shader",
      "url": "https://en.wikipedia.org/wiki/Shader"
    },
    {
      "title": "NVIDIA GeForce 8800 GTX / GTS (G80) - The World's First DX10 GPU",
      "url": "https://www.hardwarezone.com.sg/feature-nvidia-geforce-8800-gtx-gts-g80-worlds-first-dx10-gpu/embracing-unified-shader-architecture"
    },
    {
      "title": "GeForce 8 series",
      "url": "https://en.wikipedia.org/wiki/GeForce_8_series"
    },
    {
      "title": "1. Introduction — CUDA C Programming Guide",
      "url": "https://docs.nvidia.com/cuda/archive/12.3.2/cuda-c-programming-guide/index.html"
    },
    {
      "title": "Memory-Efficient Object-Oriented Programming on GPUs",
      "url": "https://arxiv.org/pdf/1908.05845"
    },
    {
      "title": "Implementing Strassen's Algorithm with CUTLASS on NVIDIA Volta GPUs",
      "url": "https://arxiv.org/pdf/1808.07984"
    },
    {
      "title": "Memory Hierarchy - SLING user documentation",
      "url": "https://doc.sling.si/en/workshops/programming-gpu-cuda/02-GPU/02-memmodel/"
    },
    {
      "title": "CUDA vs ROCm vs Vulkan vs Metal: GPU Compute in 2026",
      "url": "https://orchestrator.dev/blog/2026-05-24-gpu-compute-platforms-comparison/"
    },
    {
      "title": "Choosing Vulkan, OpenCL, SYCL or CUDA for GPU Compute",
      "url": "https://www.technolynx.com/post/choosing-vulkan-opencl-sycl-or-cuda-for-gpu-compute"
    },
    {
      "title": "General-purpose computing on graphics processing units - ArchWiki",
      "url": "https://wiki.archlinux.org/title/General-purpose_computing_on_graphics_processing_units"
    },
    {
      "title": "ROCm — Grokipedia",
      "url": "https://grokipedia.com/page/ROCm"
    },
    {
      "title": "SPIR-V on ROCm: A Portable IR for AMD GPUs — ROCm Blogs",
      "url": "https://rocm.blogs.amd.com/software-tools-optimization/spir-v-rocm/README.html"
    },
    {
      "title": "Running Local AI on AMD: ROCm, Ollama, and LM Studio Performance in 2026",
      "url": "https://www.mindstudio.ai/blog/running-local-ai-amd-rocm-ollama-lm-studio"
    },
    {
      "title": "The Origins of GPU Computing",
      "url": "https://cacm.acm.org/federal-funding-of-academic-research/the-origins-of-gpu-computing/"
    },
    {
      "title": "OCCA: A unified approach to multi-threading languages",
      "url": "https://arxiv.org/pdf/1403.0968"
    },
    {
      "title": "Rediscovering Graphic Shaders GPGPU Programming",
      "url": "https://nathan.rs/posts/gpu-shader-programming/"
    },
    {
      "title": "A Brief History and Introduction to GPGPU",
      "url": "https://jeewhanchoi.github.io/publication/pdf/brief_history.pdf"
    },
    {
      "title": "Evolution of GPU Programming",
      "url": "https://www.cloudrift.ai/blog/evolution-of-gpu-programming"
    },
    {
      "title": "NVIDIA Tensor Cores: Their Role in AI Training (October 2026)",
      "url": "https://www.thundercompute.com/blog/tensor-cores-explained-ai-training"
    },
    {
      "title": "Mixed-Precision Quantization for Language Models: Techniques and Prospects",
      "url": "https://arxiv.org/pdf/2510.16805"
    },
    {
      "title": "FP16 / BF16 / FP8: Mixed Precision Training",
      "url": "https://theneuralbase.com/nvidia-cuda-for-ai/learn/intermediate/fp16-bf16-fp8/"
    },
    {
      "title": "How FP16, BF16, and FP8 Speed Up Model Training",
      "url": "https://www.runpod.io/articles/guides/fp16-bf16-fp8-mixed-precision-speed-up-my-model-training"
    },
    {
      "title": "The Landscape of GPU-Centric Communication",
      "url": "https://arxiv.org/pdf/2409.09874"
    },
    {
      "title": "High-Speed Interconnects for GPUs",
      "url": "https://apxml.com/courses/how-to-build-a-large-language-model/chapter-18-hardware-considerations-llm-training/interconnect-technologies-nvlink-infiniband"
    },
    {
      "title": "How GPUs communicate in training cluster NVIDIA",
      "url": "https://optinest.de/ai-infrastructure/networking/interconnect/how-gpus-communicate-in-training-cluster-nvidia"
    },
    {
      "title": "High-Bandwidth Interconnects",
      "url": "https://apxml.com/courses/advanced-ai-infrastructure-design-optimization/chapter-1-architectural-patterns-ai-platforms/high-bandwidth-interconnects"
    },
    {
      "title": "AI Inference vs Training: GPU Selection and Cost",
      "url": "https://www.runpod.io/articles/guides/ai-inference-vs-training-gpu-guide"
    },
    {
      "title": "GPU Infrastructure for AI Inference: Training vs. Production",
      "url": "https://www.civo.com/blog/ai-inference-infrastructure-training-to-production"
    },
    {
      "title": "Scaling Large Language Model Training on Frontier with Low-Bandwidth Partitioning",
      "url": "https://arxiv.org/pdf/2501.04266"
    },
    {
      "title": "How NVLink Enhances Multi-GPU Performance",
      "url": "https://medium.com/@daya-shankar/how-nvlink-enhances-multi-gpu-performance-6c797f72f6d0"
    },
    {
      "title": "FP8 vs FP16 vs BF16 Precision Guide 2026",
      "url": "https://packet.ai/blog/fp8-vs-fp16-vs-bf16"
    },
    {
      "title": "FP8 Vs BF16: Choosing Mixed Precision On NVIDIA Tensor Cores",
      "url": "https://acecloud.ai/blog/fp8-vs-bf16-mixed-precision-tensor-cores/"
    },
    {
      "title": "FP8 vs FP16/BF16/INT8: Theoretical Advantages",
      "url": "https://www.rohan-paul.com/p/fp8-vs-fp16bf16int8-theoretical-advantages"
    },
    {
      "title": "AI GPU Guide: Training vs Inference Explained",
      "url": "https://www.gmicloud.ai/en/blog/how-to-choose-the-right-gpu-for-ai-training-vs-inference-2026-guide"
    },
    {
      "title": "AI Inference vs Training Infrastructure",
      "url": "https://introl.com/blog/ai-inference-vs-training-infrastructure-economics-diverging-2025"
    },
    {
      "title": "Hardware Acceleration for Neural Networks: A Comprehensive Survey",
      "url": "https://arxiv.org/pdf/2512.23914"
    },
    {
      "title": "EasyChair Preprint №13991 Accelerating Molecular Dynamics Simulations with",
      "url": "https://easychair.org/publications/preprint/GRjS/open"
    },
    {
      "title": "ddcMD: a fully GPU-accelerated molecular dynamics ...",
      "url": "https://www.osti.gov/servlets/purl/1669229"
    },
    {
      "title": "MIST: A Simple and Efficient Molecular Dynamics Abstraction Library for Integrator Development",
      "url": "https://arxiv.org/pdf/1805.07117"
    },
    {
      "title": "Accelerators for Classical Molecular Dynamics Simulations of Biomolecules",
      "url": "https://pubs.acs.org/doi/10.1021/acs.jctc.1c01214"
    },
    {
      "title": "Parallel CT image reconstruction based on GPUs - ScienceDirect",
      "url": "https://www.sciencedirect.com/science/article/abs/pii/S0969806X13001436"
    },
    {
      "title": "GPU-Based 3D Cone-Beam CT Image Reconstruction for Large Data Volume",
      "url": "https://www.ncbi.nlm.nih.gov/pmc/articles/PMC2734932/"
    },
    {
      "title": "Accelerating advanced mri reconstructions on gpus",
      "url": "https://dl.acm.org/doi/10.1145/1366230.1366276"
    },
    {
      "title": "Edge GPU Aware Multiple AI Model Pipeline for Accelerated MRI Reconstruction and Analysis",
      "url": "https://arxiv.org/pdf/2510.01730"
    },
    {
      "title": "Real Time Cluster Path Tracing",
      "url": "https://arxiv.org/pdf/2110.08913"
    },
    {
      "title": "Rendering (computer graphics)",
      "url": "https://en.wikipedia.org/wiki/Rendering_(computer_graphics)"
    },
    {
      "title": "New NVIDIA Path Tracing Breakthrough Interactively Renders 7,000 Dynamic Lights",
      "url": "https://developer.nvidia.com/blog/turning-up-the-lights-interactive-path-tracing-scenes-from-a-short-film/"
    },
    {
      "title": "Omniverse RTX Renderer — Omniverse Materials and Rendering",
      "url": "https://docs.omniverse.nvidia.com/materials-and-rendering/latest/rtx-renderer.html"
    },
    {
      "title": "Nvidia GPU Market Share 2026: Discrete AIB, AI Data Center, and Gaming Installed Base - Axis Intelligence",
      "url": "https://axis-intelligence.com/nvidia-gpu-market-share/"
    },
    {
      "title": "AMD GPU Market Share 2026: How AMD Is Competing With NVIDIA and Intel - Thinkofgames",
      "url": "https://thinkofgames.com/amd-gpu-market-share-2026-how-amd-is-competing-with-nvidia-and-intel/"
    },
    {
      "title": "AI GPU Market Share NVIDIA vs AMD vs Intel: 2026 Statistics",
      "url": "https://commandlinux.com/statistics/ai-gpu-market-share-nvidia-vs-amd-vs-intel/"
    },
    {
      "title": "AI and Packaging Bottleneck, Part 1: TSMC - Technosight",
      "url": "https://technosight.substack.com/p/ai-and-packaging-bottleneck-part"
    },
    {
      "title": "Intel vs TSMC: How CoWoS Packaging Constraints Could ...",
      "url": "https://io-fund.com/ai-stocks/intel-vs-tsmc-cowos-constraints-intel-foundry"
    },
    {
      "title": "Nvidia snaps up AI chip packaging capacity as TSMC expands in U.S.",
      "url": "https://www.cnbc.com/2026/04/08/tsmc-nvidia-advanced-packaging-intel.html"
    },
    {
      "title": "Advanced Packaging Is the Latest AI Bottleneck - Domino Theory",
      "url": "https://dominotheory.com/advanced-packaging-is-the-latest-ai-bottleneck/"
    },
    {
      "title": "TSMC Boosts CoWoS Capacity as NVIDIA Dominates Advanced Packaging Orders through 2027",
      "url": "https://markets.financialcontent.com/wral/article/tokenring-2025-12-26-tsmc-boosts-cowos-capacity-as-nvidia-dominates-advanced-packaging-orders-through-2027"
    },
    {
      "title": "TSMC Advanced Packaging Bottleneck: Why CoWoS Controls AI Chip Supply",
      "url": "https://nextwavesinsight.com/tsmc-advanced-packaging-nvidia-ai-supply-chain-2026/"
    },
    {
      "title": "TSMC CoWoS Hidden Bottleneck & AI Chip Supply Squeeze",
      "url": "https://www.indmoney.com/blog/us-stocks/tsmc-cowos-bottleneck-ai-chip-supply-squeeze-explained"
    },
    {
      "title": "Data Center GPU Pricing 2026: The Full AI Pricing Index",
      "url": "https://intuitionlabs.ai/articles/data-center-gpu-pricing-2026"
    },
    {
      "title": "Why AI GPU Prices Are Rising in 2026: HBM Shortage Explained",
      "url": "https://gpusmith.com/articles/en/ai-gpu-prices-rising-hbm-memory-shortage"
    },
    {
      "title": "Gaming GPU Prices 2026: RTX 5090 Tops $5,000 - Tech Insider",
      "url": "https://tech-insider.org/gpu-prices-2026/"
    },
    {
      "title": "Why Are GPU Prices Rising? The Truth About Memory Costs in 2026 - Tech News - darkFlash",
      "url": "https://www.darkflash.com/article/why-are-gpu-prices-rising-memory-costs-2026"
    },
    {
      "title": "NVIDIA Commands Over 80 Percent of the AI GPU Market Share in 2026 Amid Growing Rivalry",
      "url": "https://learn.oreateai.com/learn/nvidia-commands-over-80-percent-of-the-ai-gpu-market-share-in-2026-amid-growing-rivalry"
    },
    {
      "title": "AMD vs NVIDIA vs Intel: Best semiconductor stock 2026",
      "url": "https://www.winvesta.in/blog/investors/amd-vs-nvidia-vs-intel-best-semiconductor-stock-2026"
    },
    {
      "title": "NVIDIA Grabs 90% GPU Share as Shipments Hit 12.5M [2026]",
      "url": "https://tech-insider.org/nvidia-90-percent-gpu-market-share-shipments-2026/"
    },
    {
      "title": "A GPU Memory Crisis Is Wrecking Every 2026 Build List",
      "url": "https://techguided.com/a-gpu-memory-crisis-is-wrecking-every-2026-build-list"
    },
    {
      "title": "Why GPU Prices Are Climbing Again in 2026: The Memory Shortage Explained",
      "url": "https://pcgamecheck.com/blog/why-gpus-expensive-2026-memory-shortage-explained"
    },
    {
      "title": "The Crypto Crash is Sinking GPU Prices as Mining Profitability Plummets - AiCoin",
      "url": "https://www.aicoin.com/en/article/304524"
    },
    {
      "title": "With Revenue Share Shrinking, Does Nvidia Need Gaming Anymore?",
      "url": "https://finance.yahoo.com/news/revenue-share-shrinking-does-nvidia-163626108.html"
    },
    {
      "title": "Factors that affect the price of GPUs [AI Impacts Wiki]",
      "url": "https://wiki.aiimpacts.org/ai_timelines/hardware_and_ai_timelines/factors_that_affect_gpu_price"
    },
    {
      "title": "GPU Price Drop Crypto Mining Slow Down News",
      "url": "https://hypebeast.com/2022/7/gpu-price-drop-cryptocurrency-mining-slow-down-news"
    },
    {
      "title": "The Crypto Crash is Sinking GPU Prices as Mining Profitability Plummets - Decrypt",
      "url": "https://decrypt.co/103400/the-crypto-market-crash-is-bringing-down-the-cost-of-gpus"
    },
    {
      "title": "How Graphics Card Prices Spiraled: Mining, Scalpers, and Prices No One Could Believe",
      "url": "https://vgtimes.com/articles/169570-how-graphics-card-prices-spiraled.html"
    },
    {
      "title": "NVIDIA CORP - Form 8-K - FY2022",
      "url": "https://www.sec.gov/Archives/edgar/data/1045810/000104581022000136/q2fy23cfocommentary.htm"
    },
    {
      "title": "Nvidia says it raked in $193.7 billion in annual data center revenue over the last year, while gaming brought in $16 billion",
      "url": "https://finance.yahoo.com/news/nvidia-says-raked-193-7-122030298.html"
    },
    {
      "title": "GPU pricing set for reset as AI-driven memory shortages push costs sharply higher - Astute Group",
      "url": "https://www.astutegroup.com/news/general/gpu-pricing-set-for-reset-as-ai-driven-memory-shortages-push-costs-sharply-higher/"
    },
    {
      "title": "GPU Price Increase 2026: Nvidia, AMD Hike Kit Costs",
      "url": "https://tech-insider.org/gpu-price-increase-2026/"
    },
    {
      "title": "Nvidia RTX 5090 Tops $5,000 as GPU Prices Jump 39% [2026]",
      "url": "https://tech-insider.org/nvidia-gpu-price-hike-rtx-50-series-2026/"
    },
    {
      "title": "Nvidia GPU Prices Surge 41% in Europe [2026]",
      "url": "https://shattered.io/nvidia-amd-gpu-prices-surge-europe-2026/"
    },
    {
      "title": "How Many Watts Does a GPU Use? (Complete Power Consumption Guide) -",
      "url": "https://techiher.com/how-many-watts-does-a-gpu-use/"
    },
    {
      "title": "Best Graphics Cards for Gaming in 2026",
      "url": "https://www.tomshardware.com/reviews/best-gpus,4380.html"
    },
    {
      "title": "Gaming & Workstation PSU Guide 2026",
      "url": "https://www.newegg.com/insider/powering-gaming-and-professional-workstations-in-2026-psu-requirements-for-high-performance-systems/"
    },
    {
      "title": "GPU Efficiency Chart 2026: Performance Per Watt Rankings",
      "url": "https://www.maxmybuild.com/benchmarks/gpu-performance-per-watt"
    },
    {
      "title": "AI Data Center Power: 415 TWh in 2024, 945 TWh by 2030",
      "url": "https://www.aitooldiscovery.com/ai-infra/ai-data-center-power-consumption"
    },
    {
      "title": "AI Data Center Energy Consumption Statistics 2026: The Definitive Data Report - Axis Intelligence",
      "url": "https://axis-intelligence.com/ai-data-center-energy-consumption-statistics/"
    },
    {
      "title": "AI Energy Statistics (2026): 45+ Data Points on Data Center Power, Per-Query Cost, and Grid Strain — VoxBooster",
      "url": "https://voxbooster.com/blog/ai-energy-statistics-2026/"
    },
    {
      "title": "US AI Power Demand 2026, $500B Deloitte Forecast - EnkiAI",
      "url": "https://enkiai.com/data-center/ai-gpu-infrastructure-market/"
    },
    {
      "title": "How Upscaling Works, and Why DLSS Still Edges Out FSR - Cheat Code Central",
      "url": "https://www.cheatcc.com/articles/how-upscaling-works-and-why-dlss-still-edges-out-fsr/"
    },
    {
      "title": "Deep learning based selection of samples for adaptive supersampling",
      "url": "https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/11526964"
    },
    {
      "title": "GPU TDP & Power Consumption Explained (SA 2026)",
      "url": "https://www.evetech.co.za/gpu-tdp-power-consumption-explained/e/3694"
    },
    {
      "title": "Best GPU for Gaming in 2026",
      "url": "https://www.eneba.com/hub/gaming-gear/best-gpu-for-gaming/"
    },
    {
      "title": "How Much Power Supply Wattage Does a Gaming PC Need in 2026?",
      "url": "https://seasonic.com/insights/psu-wattage-for-gaming-pc-2026/"
    },
    {
      "title": "Best Graphics Cards for Gaming in 2026",
      "url": "https://ai2.work/blog/gpu-strategy-for-2026-navigating-feature-parity-and-memory-scaling-in-the-gaming-landscape"
    },
    {
      "title": "How much energy do data centers and artificial intelligence use?",
      "url": "https://ourworldindata.org/how-much-energy-do-data-centers-and-artificial-intelligence-use"
    },
    {
      "title": "AI Data Center Power Demand 2026: 1,000 TWh, 41 GW US Load",
      "url": "https://valueaddvc.com/blog/ai-data-center-power-demand-how-much-electricity-ai-actually-consumes-in-2026"
    },
    {
      "title": "Power Requirements for AI Data Centers (2026): Complete Guide",
      "url": "https://techplustrends.com/power-requirements-ai-data-centers/"
    },
    {
      "title": "DLSS Explained: What Is It and Should You Use It SA",
      "url": "https://www.evetech.co.za/dlss-explained-what-is-it/e/3690"
    },
    {
      "title": "I moved one thing in DLSS 5's pipeline, and it gave me back 50% of my frame rate",
      "url": "https://www.xda-developers.com/i-moved-dlss-5-pipeline-in-optiscaler-and-got-back-50-of-my-frame-rate/"
    }
  ],
  "license": "https://creativecommons.org/licenses/by/4.0/"
}